2010-06-08 16:31:28 -07:00
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;
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; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
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;
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2010-09-09 05:06:21 -07:00
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; Use of this source code is governed by a BSD-style license
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2010-06-08 16:31:28 -07:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-09-09 05:06:21 -07:00
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; in the file PATENTS. All contributing project authors may
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2010-06-08 16:31:28 -07:00
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; be found in the AUTHORS file in the root of the source tree.
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;
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%include "vpx_ports/x86_abi_support.asm"
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;void vp8_short_inv_walsh4x4_1_mmx(short *input, short *output)
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global sym(vp8_short_inv_walsh4x4_1_mmx)
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sym(vp8_short_inv_walsh4x4_1_mmx):
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push rbp
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mov rbp, rsp
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SHADOW_ARGS_TO_STACK 2
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push rsi
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push rdi
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; end prolog
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mov rsi, arg(0)
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mov rax, 3
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mov rdi, arg(1)
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add rax, [rsi] ;input[0] + 3
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movd mm0, eax
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punpcklwd mm0, mm0 ;x x val val
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punpckldq mm0, mm0 ;val val val val
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psraw mm0, 3 ;(input[0] + 3) >> 3
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movq [rdi + 0], mm0
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movq [rdi + 8], mm0
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movq [rdi + 16], mm0
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movq [rdi + 24], mm0
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; begin epilog
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pop rdi
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pop rsi
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UNSHADOW_ARGS
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pop rbp
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ret
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;void vp8_short_inv_walsh4x4_mmx(short *input, short *output)
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global sym(vp8_short_inv_walsh4x4_mmx)
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sym(vp8_short_inv_walsh4x4_mmx):
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push rbp
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mov rbp, rsp
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SHADOW_ARGS_TO_STACK 2
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push rsi
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push rdi
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; end prolog
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mov rax, 3
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mov rsi, arg(0)
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mov rdi, arg(1)
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shl rax, 16
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movq mm0, [rsi + 0] ;ip[0]
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movq mm1, [rsi + 8] ;ip[4]
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or rax, 3 ;00030003h
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movq mm2, [rsi + 16] ;ip[8]
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movq mm3, [rsi + 24] ;ip[12]
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movd mm7, rax
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movq mm4, mm0
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punpcklwd mm7, mm7 ;0003000300030003h
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movq mm5, mm1
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paddw mm4, mm3 ;ip[0] + ip[12] aka al
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paddw mm5, mm2 ;ip[4] + ip[8] aka bl
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movq mm6, mm4 ;temp al
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paddw mm4, mm5 ;al + bl
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psubw mm6, mm5 ;al - bl
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psubw mm0, mm3 ;ip[0] - ip[12] aka d1
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psubw mm1, mm2 ;ip[4] - ip[8] aka c1
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movq mm5, mm0 ;temp dl
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paddw mm0, mm1 ;dl + cl
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psubw mm5, mm1 ;dl - cl
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; 03 02 01 00
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; 13 12 11 10
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; 23 22 21 20
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; 33 32 31 30
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movq mm3, mm4 ; 03 02 01 00
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punpcklwd mm4, mm0 ; 11 01 10 00
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punpckhwd mm3, mm0 ; 13 03 12 02
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movq mm1, mm6 ; 23 22 21 20
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punpcklwd mm6, mm5 ; 31 21 30 20
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punpckhwd mm1, mm5 ; 33 23 32 22
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movq mm0, mm4 ; 11 01 10 00
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movq mm2, mm3 ; 13 03 12 02
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punpckldq mm0, mm6 ; 30 20 10 00 aka ip[0]
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punpckhdq mm4, mm6 ; 31 21 11 01 aka ip[4]
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punpckldq mm2, mm1 ; 32 22 12 02 aka ip[8]
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punpckhdq mm3, mm1 ; 33 23 13 03 aka ip[12]
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;~~~~~~~~~~~~~~~~~~~~~
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movq mm1, mm0
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movq mm5, mm4
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paddw mm1, mm3 ;ip[0] + ip[12] aka al
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paddw mm5, mm2 ;ip[4] + ip[8] aka bl
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movq mm6, mm1 ;temp al
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paddw mm1, mm5 ;al + bl
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psubw mm6, mm5 ;al - bl
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psubw mm0, mm3 ;ip[0] - ip[12] aka d1
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psubw mm4, mm2 ;ip[4] - ip[8] aka c1
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movq mm5, mm0 ;temp dl
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paddw mm0, mm4 ;dl + cl
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psubw mm5, mm4 ;dl - cl
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;~~~~~~~~~~~~~~~~~~~~~
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movq mm3, mm1 ; 03 02 01 00
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punpcklwd mm1, mm0 ; 11 01 10 00
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punpckhwd mm3, mm0 ; 13 03 12 02
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movq mm4, mm6 ; 23 22 21 20
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punpcklwd mm6, mm5 ; 31 21 30 20
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punpckhwd mm4, mm5 ; 33 23 32 22
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movq mm0, mm1 ; 11 01 10 00
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movq mm2, mm3 ; 13 03 12 02
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punpckldq mm0, mm6 ; 30 20 10 00 aka ip[0]
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punpckhdq mm1, mm6 ; 31 21 11 01 aka ip[4]
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punpckldq mm2, mm4 ; 32 22 12 02 aka ip[8]
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punpckhdq mm3, mm4 ; 33 23 13 03 aka ip[12]
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paddw mm0, mm7
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paddw mm1, mm7
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paddw mm2, mm7
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paddw mm3, mm7
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psraw mm0, 3
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psraw mm1, 3
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psraw mm2, 3
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psraw mm3, 3
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movq [rdi + 0], mm0
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movq [rdi + 8], mm1
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movq [rdi + 16], mm2
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movq [rdi + 24], mm3
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; begin epilog
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pop rdi
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pop rsi
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UNSHADOW_ARGS
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pop rbp
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ret
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