Emil Renner Berthing 68d90e8ea2 riscv: Implement non-coherent DMA support via SiFive cache flushing ...

This variant is used on the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>

2022-10-20 17:50:57 +02:00

..

cacheflush.c

RISC-V: Do not use cpumask data structure for hartid bitmap

2022-01-20 09:27:22 -08:00

context.c

riscv: Implement sv48 support

2022-01-19 17:54:09 -08:00

dma-noncoherent.c

riscv: Implement non-coherent DMA support via SiFive cache flushing

2022-10-20 17:50:57 +02:00

extable.c

riscv: extable: fix err reg writing in dedicated uaccess handler

2022-02-08 17:02:47 -08:00

fault.c

riscv: Make VM_WRITE imply VM_READ

2022-09-22 09:44:50 -07:00

hugetlbpage.c

hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate

2020-06-03 20:09:46 -07:00

init.c

RISC-V: fixups to work with crash tool

2022-08-11 09:04:01 -07:00

kasan_init.c

Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2022-03-25 10:11:38 -07:00

Makefile

riscv: Add support for non-coherent devices using zicbom extension

2022-07-28 15:30:51 -07:00

pageattr.c

mm: pagewalk: Fix race between unmap and page walker

2022-09-03 10:13:13 -07:00

physaddr.c

riscv: Fix DEBUG_VIRTUAL false warnings

2022-03-03 15:32:04 -08:00

ptdump.c

riscv: Fix PTDUMP output now BPF region moved back to module region

2021-07-06 15:21:27 -07:00

tlbflush.c

RISC-V: Do not use cpumask data structure for hartid bitmap

2022-01-20 09:27:22 -08:00