Pull irq domain ARM updates from Thomas Gleixner:
"This set of changes make use of hierarchical irqdomains to provide:
- MSI/ITS support for GICv3
- MSI support for GICv2m
- Interrupt polarity extender for GICv1
Marc has come more cleanups for the existing extension hooks of GIC in
the pipeline, but they are going to be 3.20 material"
* 'irq-irqdomain-arm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (22 commits)
irqchip: gicv3-its: Fix ITT allocation
irqchip: gicv3-its: Move some alloc/free code to activate/deactivate
irqchip: gicv3-its: Fix domain free in multi-MSI case
irqchip: gic: Remove warning by including linux/irqdomain.h
irqchip: gic-v2m: Add DT bindings for GICv2m
irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell
irqchip: mtk-sysirq: dt-bindings: Add bindings for mediatek sysirq
irqchip: mtk-sysirq: Add sysirq interrupt polarity support
irqchip: gic: Support hierarchy irq domain.
irqchip: GICv3: Binding updates for ITS
irqchip: GICv3: ITS: enable compilation of the ITS driver
irqchip: GICv3: ITS: plug ITS init into main GICv3 code
irqchip: GICv3: ITS: DT probing and initialization
irqchip: GICv3: ITS: MSI support
irqchip: GICv3: ITS: device allocation and configuration
irqchip: GICv3: ITS: tables allocators
irqchip: GICv3: ITS: LPI allocator
irqchip: GICv3: ITS: irqchip implementation
irqchip: GICv3: ITS command queue
irqchip: GICv3: rework redistributor structure
...
Commit
853a33ce69 irqchip: gic-v2m: Add support for ARM GICv2m MSI(-X) doorbell
Introduced a series of warnings when building ARM multi_v7_defconfig:
include/linux/irqchip/arm-gic.h:109:53: warning: its scope is only this definition or declaration, which is probably not what you want
In file included from arch/arm/mach-ux500/pm.c:13:0:
include/linux/irqchip/arm-gic.h:109:53: warning: 'struct irq_domain' declared inside parameter list
int gicv2m_of_init(struct device_node *node, struct irq_domain *parent);
^
Fix this by adding the proper include.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
[ jac merged much more correct version from Marc into this patch ]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Link: https://lkml.kernel.org/r/1417170975-1163-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pull irq updates from Thomas Gleixner:
"The irq departement delivers:
- a cleanup series to get rid of mindlessly copied code.
- another bunch of new pointlessly different interrupt chip drivers.
Adding homebrewn irq chips (and timers) to SoCs must provide a
value add which is beyond the imagination of mere mortals.
- the usual SoC irq controller updates, IOW my second cat herding
project"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (44 commits)
irqchip: gic-v3: Implement CPU PM notifier
irqchip: gic-v3: Refactor gic_enable_redist to support both enabling and disabling
irqchip: renesas-intc-irqpin: Add minimal runtime PM support
irqchip: renesas-intc-irqpin: Add helper variable dev = &pdev->dev
irqchip: atmel-aic5: Add sama5d4 support
irqchip: atmel-aic5: The sama5d3 has 48 IRQs
Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding
irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller
irqchip: renesas-irqc: Add binding docs for new R-Car Gen2 SoCs
irqchip: renesas-irqc: Add DT binding documentation
irqchip: renesas-intc-irqpin: Document SoC-specific bindings
openrisc: Get rid of handle_IRQ
arm64: Get rid of handle_IRQ
ARM: omap2: irq: Convert to handle_domain_irq
ARM: imx: tzic: Convert to handle_domain_irq
ARM: imx: avic: Convert to handle_domain_irq
irqchip: or1k-pic: Convert to handle_domain_irq
irqchip: atmel-aic5: Convert to handle_domain_irq
irqchip: atmel-aic: Convert to handle_domain_irq
irqchip: gic-v3: Convert to handle_domain_irq
...
OMAP INTC irqchip driver will be moved under
drivers/irqchip/ soon but we still have a dependency
with mach-omap2 when it comes to idle functions.
In order to make it easy to share those function
prototypes with OMAP PM code, we introduce this new
header.
To avoid modifying several board-files and some of
the PM-related code, we just include the new header
from common.h which was already included by all
users of IRQ-related PM code.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This change is made to preserve the GIC v2 bypass bits in the
GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec).
This code will preserve all bits configured by the bootloader regarding
v2 bypass group bits. In the X-Gene platform, the bypass functionality
is not used and bypass bits should not be changed by the kernel gic
code as it could lead to incorrect behavior.
Signed-off-by: Feng Kan <fkan@apm.com>
Reviewed-by: Vinayak Kale <vkale@apm.com>
Reviewed-by: Anup Patel <apatel@apm.com>
Link: https://lkml.kernel.org/r/1406757419-18729-3-git-send-email-fkan@apm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Pull irq updates from Thomas Gleixner:
"Nothing spectacular from the irq department this time:
- overhaul of the crossbar chip driver
- overhaul of the spear shirq chip driver
- support for the atmel-aic chip
- code move from arch to drivers
- the usual tiny fixlets
- two reverts worth to mention which undo the too simple attempt of
supporting wakeup interrupts on shared interrupt lines"
* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (41 commits)
Revert "irq: Warn when shared interrupts do not match on NO_SUSPEND"
Revert "PM / sleep / irq: Do not suspend wakeup interrupts"
irq: Warn when shared interrupts do not match on NO_SUSPEND
irqchip: atmel-aic: Define irq fixups for atmel SoCs
irqchip: atmel-aic: Implement RTC irq fixup
irqchip: atmel-aic: Add irq fixup infrastructure
irqchip: atmel-aic: Add atmel AIC/AIC5 drivers
irqchip: atmel-aic: Move binding doc to interrupt-controller directory
genirq: generic chip: Export irq_map_generic_chip function
PM / sleep / irq: Do not suspend wakeup interrupts
irqchip: or1k-pic: Migrate from arch/openrisc/
irqchip: crossbar: Allow for quirky hardware with direct hardwiring of GIC
documentation: dt: omap: crossbar: Add description for interrupt consumer
irqchip: crossbar: Introduce centralized check for crossbar write
irqchip: crossbar: Introduce ti, max-crossbar-sources to identify valid crossbar mapping
irqchip: crossbar: Add kerneldoc for crossbar_domain_unmap callback
irqchip: crossbar: Set cb pointer to null in case of error
irqchip: crossbar: Change the goto naming
irqchip: crossbar: Return proper error value
irqchip: crossbar: Fix kerneldoc warning
...
GICv3 introduces new system registers accessible with the full msr/mrs
syntax (e.g. mrs x0, Sop0_op1_CRm_CRn_op2). However, only recent
binutils understand the new syntax. This patch introduces msr_s/mrs_s
assembly macros which generate the equivalent instructions above and
converts the existing GICv3 code (both drivers/irqchip/ and
arch/arm64/kernel/).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Olof Johansson <olof@lixom.net>
Tested-by: Olof Johansson <olof@lixom.net>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Merge OMAP crossbar support from Tony Lindgren:
Add support for GIC crossbar that routes interrupts on newer omaps.
Looks like people wanted these merged via the omap tree as it's
the only user for the GIC crossbar.
* tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: DRA: Enable Crossbar IP support for DRA7XX
ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number
DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP
DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs
Signed-off-by: Olof Johansson <olof@lixom.net>
This adds support for a VIC to be cascaded off another IRQ.
On the Integrator/AP logical module IM-PD1 there is a VIC
cascaded off the central FPGA IRQ controller so this is
needed for that to work out.
In order for the plug-in board to be able to register all
the devices with their IRQs relative to the offset of the
base obtained for the cascaded VIC, the base IRQ number
is passed back to the caller.
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some socs have a large number of interrupts requests to service
the needs of its many peripherals and subsystems. All of the
interrupt lines from the subsystems are not needed at the same
time, so they have to be muxed to the irq-controller appropriately.
In such places a interrupt controllers are preceded by an CROSSBAR
that provides flexibility in muxing the device requests to the controller
inputs.
This driver takes care a allocating a free irq and then configuring the
crossbar IP as a part of the mpu's irqchip callbacks. crossbar_init should
be called right before the irqchip_init, so that it is setup to handle the
irqchip callbacks.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Acked-by: Kumar Gala <galak@codeaurora.org> (for DT binding portion)
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
In some socs the gic can be preceded by a crossbar IP which
routes the peripheral interrupts to the gic inputs. The peripheral
interrupts are associated with a fixed crossbar input line and the
crossbar routes that to one of the free gic input line.
The DT entries for peripherals provides the fixed crossbar input line
as its interrupt number and the mapping code should associate this with
a free gic input line. This patch adds the support inside the gic irqchip
to handle such routable irqs. The routable irqs are registered in a linear
domain. The registered routable domain's callback should be implemented
to get a free irq and to configure the IP to route it.
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Pull Xtensa patches from Chris Zankel:
"The major changes are adding support for SMP for Xtensa, fixing and
cleaning up the ISS (simulator) network driver, and better support for
device trees"
* tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux: (40 commits)
xtensa: implement ndelay
xtensa: clean up udelay
xtensa: enable HAVE_PERF_EVENTS
xtensa: remap io area defined in device tree
xtensa: support default device tree buses
xtensa: initialize device tree clock sources
xtensa: xtfpga: fix definitions of platform devices
xtensa: standardize devicetree cpu compatible strings
xtensa: avoid duplicate of IO range definitions
xtensa: fix ATOMCTL register documentation
xtensa: Enable irqs after cpu is set online
xtensa: ISS: raise network polling rate to 10 times/sec
xtensa: remove unused XTENSA_ISS_NETWORK Kconfig parameter
xtensa: ISS: avoid simple_strtoul usage
xtensa: Switch to sched_clock_register()
xtensa: implement CPU hotplug
xtensa: add SMP support
xtensa: add MX irqchip
xtensa: clear timer IRQ unconditionally in its handler
xtensa: clean up do_interrupt/do_IRQ
...
