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Linus Torvalds d0a231f01e Merge tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 
Pull pci updates from Bjorn Helgaas:
 "Enumeration:
   - Use pci_find_vsec_capability() instead of open-coding it (Andy
     Shevchenko)
   - Convert pci_dev_present() stub from macro to static inline to avoid
     'unused variable' errors (Hans de Goede)
   - Convert sysfs slot attributes from default_attrs to default_groups
     (Greg Kroah-Hartman)
   - Use DWORD accesses for LTR, L1 SS to avoid BayHub OZ711LV2 erratum
     (Rajat Jain)
   - Remove unnecessary initialization of static variables (Longji Guo)

  Resource management:
   - Always write Intel I210 ROM BAR on update to work around device
     defect (Bjorn Helgaas)

  PCIe native device hotplug:
   - Fix pciehp lockdep errors on Thunderbolt undock (Hans de Goede)
   - Fix infinite loop in pciehp IRQ handler on power fault (Lukas
     Wunner)

  Power management:
   - Convert amd64-agp, sis-agp, via-agp from legacy PCI power
     management to generic power management (Vaibhav Gupta)

  IOMMU:
   - Add function 1 DMA alias quirk for Marvell 88SE9125 SATA controller
     so it can work with an IOMMU (Yifeng Li)

  Error handling:
   - Add PCI_ERROR_RESPONSE and related definitions for signaling and
     checking for transaction errors on PCI (Naveen Naidu)
   - Fabricate PCI_ERROR_RESPONSE data (~0) in config read wrappers,
     instead of in host controller drivers, when transactions fail on
     PCI (Naveen Naidu)
   - Use PCI_POSSIBLE_ERROR() to check for possible failure of config
     reads (Naveen Naidu)

  Peer-to-peer DMA:
   - Add Logan Gunthorpe as P2PDMA maintainer (Bjorn Helgaas)

  ASPM:
   - Calculate link L0s and L1 exit latencies when needed instead of
     caching them (Saheed O. Bolarinwa)
   - Calculate device L0s and L1 acceptable exit latencies when needed
     instead of caching them (Saheed O. Bolarinwa)
   - Remove struct aspm_latency since it's no longer needed (Saheed O.
     Bolarinwa)

  APM X-Gene PCIe controller driver:
   - Fix IB window setup, which was broken by the fact that IB resources
     are now sorted in address order instead of DT dma-ranges order (Rob
     Herring)

  Apple PCIe controller driver:
   - Enable clock gating to save power (Hector Martin)
   - Fix REFCLK1 enable/poll logic (Hector Martin)

  Broadcom STB PCIe controller driver:
   - Declare bitmap correctly for use by bitmap interfaces (Christophe
     JAILLET)
   - Clean up computation of legacy and non-legacy MSI bitmasks (Florian
     Fainelli)
   - Update suspend/resume/remove error handling to warn about errors
     and not fail the operation (Jim Quinlan)
   - Correct the "pcie" and "msi" interrupt descriptions in DT binding
     (Jim Quinlan)
   - Add DT bindings for endpoint voltage regulators (Jim Quinlan)
   - Split brcm_pcie_setup() into two functions (Jim Quinlan)
   - Add mechanism for turning on voltage regulators for connected
     devices (Jim Quinlan)
   - Turn voltage regulators for connected devices on/off when bus is
     added or removed (Jim Quinlan)
   - When suspending, don't turn off voltage regulators for wakeup
     devices (Jim Quinlan)

  Freescale i.MX6 PCIe controller driver:
   - Add i.MX8MM support (Richard Zhu)

  Freescale Layerscape PCIe controller driver:
   - Use DWC common ops instead of layerscape-specific link-up functions
     (Hou Zhiqiang)

  Intel VMD host bridge driver:
   - Honor platform ACPI _OSC feature negotiation for Root Ports below
     VMD (Kai-Heng Feng)
   - Add support for Raptor Lake SKUs (Karthik L Gopalakrishnan)
   - Reset everything below VMD before enumerating to work around
     failure to enumerate NVMe devices when guest OS reboots (Nirmal
     Patel)

  Bridge emulation (used by Marvell Aardvark and MVEBU):
   - Make emulated ROM BAR read-only by default (Pali Rohár)
   - Make some emulated legacy PCI bits read-only for PCIe devices (Pali
     Rohár)
   - Update reserved bits in emulated PCIe Capability (Pali Rohár)
   - Allow drivers to emulate different PCIe Capability versions (Pali
     Rohár)
   - Set emulated Capabilities List bit for all PCIe devices, since they
     must have at least a PCIe Capability (Pali Rohár)

  Marvell Aardvark PCIe controller driver:
   - Add bridge emulation definitions for PCIe DEVCAP2, DEVCTL2,
     DEVSTA2, LNKCAP2, LNKCTL2, LNKSTA2, SLTCAP2, SLTCTL2, SLTSTA2 (Pali
     Rohár)
   - Add aardvark support for DEVCAP2, DEVCTL2, LNKCAP2 and LNKCTL2
     registers (Pali Rohár)
   - Clear all MSIs at setup to avoid spurious interrupts (Pali Rohár)
   - Disable bus mastering when unbinding host controller driver (Pali
     Rohár)
   - Mask all interrupts when unbinding host controller driver (Pali
     Rohár)
   - Fix memory leak in host controller unbind (Pali Rohár)
   - Assert PERST# when unbinding host controller driver (Pali Rohár)
   - Disable link training when unbinding host controller driver (Pali
     Rohár)
   - Disable common PHY when unbinding host controller driver (Pali
     Rohár)
   - Fix resource type checking to check only IORESOURCE_MEM, not
     IORESOURCE_MEM_64, which is a flavor of IORESOURCE_MEM (Pali Rohár)

  Marvell MVEBU PCIe controller driver:
   - Implement pci_remap_iospace() for ARM so mvebu can use
     devm_pci_remap_iospace() instead of the previous ARM-specific
     pci_ioremap_io() interface (Pali Rohár)
   - Use the standard pci_host_probe() instead of the device-specific
     mvebu_pci_host_probe() (Pali Rohár)
   - Replace all uses of ARM-specific pci_ioremap_io() with the ARM
     implementation of the standard pci_remap_iospace() interface and
     remove pci_ioremap_io() (Pali Rohár)
   - Skip initializing invalid Root Ports (Pali Rohár)
   - Check for errors from pci_bridge_emul_init() (Pali Rohár)
   - Ignore any bridges at non-zero function numbers (Pali Rohár)
   - Return ~0 data for invalid config read size (Pali Rohár)
   - Disallow mapping interrupts on emulated bridges (Pali Rohár)
   - Clear Root Port Memory & I/O Space Enable and Bus Master Enable at
     initialization (Pali Rohár)
   - Make type bits in Root Port I/O Base register read-only (Pali
     Rohár)
   - Disable Root Port windows when base/limit set to invalid values
     (Pali Rohár)
   - Set controller to Root Complex mode (Pali Rohár)
   - Set Root Port Class Code to PCI Bridge (Pali Rohár)
   - Update emulated Root Port secondary bus numbers to better reflect
     the actual topology (Pali Rohár)
   - Add PCI_BRIDGE_CTL_BUS_RESET support to emulated Root Ports so
     pci_reset_secondary_bus() can reset connected devices (Pali Rohár)
   - Add PCI_EXP_DEVCTL Error Reporting Enable support to emulated Root
     Ports (Pali Rohár)
   - Add PCI_EXP_RTSTA PME Status bit support to emulated Root Ports
     (Pali Rohár)
   - Add DEVCAP2, DEVCTL2 and LNKCTL2 support to emulated Root Ports on
     Armada XP and newer devices (Pali Rohár)
   - Export mvebu-mbus.c symbols to allow pci-mvebu.c to be a module
     (Pali Rohár)
   - Add support for compiling as a module (Pali Rohár)

  MediaTek PCIe controller driver:
   - Assert PERST# for 100ms to allow power and clock to stabilize
     (qizhong cheng)

  MediaTek PCIe Gen3 controller driver:
   - Disable Mediatek DVFSRC voltage request since lack of DVFSRC to
     respond to the request causes failure to exit L1 PM Substate
     (Jianjun Wang)

  MediaTek MT7621 PCIe controller driver:
   - Declare mt7621_pci_ops static (Sergio Paracuellos)
   - Give pcibios_root_bridge_prepare() access to host bridge windows
     (Sergio Paracuellos)
   - Move MIPS I/O coherency unit setup from driver to
     pcibios_root_bridge_prepare() (Sergio Paracuellos)
   - Add missing MODULE_LICENSE() (Sergio Paracuellos)
   - Allow COMPILE_TEST for all arches (Sergio Paracuellos)

  Microsoft Hyper-V host bridge driver:
   - Add hv-internal interfaces to encapsulate arch IRQ dependencies
     (Sunil Muthuswamy)
   - Add arm64 Hyper-V vPCI support (Sunil Muthuswamy)

  Qualcomm PCIe controller driver:
   - Undo PM setup in qcom_pcie_probe() error handling path (Christophe
     JAILLET)
   - Use __be16 type to store return value from cpu_to_be16()
     (Manivannan Sadhasivam)
   - Constify static dw_pcie_ep_ops (Rikard Falkeborn)

  Renesas R-Car PCIe controller driver:
   - Fix aarch32 abort handler so it doesn't check the wrong bus clock
     before accessing the host controller (Marek Vasut)

  TI Keystone PCIe controller driver:
   - Add register offset for ti,syscon-pcie-id and ti,syscon-pcie-mode
     DT properties (Kishon Vijay Abraham I)

  MicroSemi Switchtec management driver:
   - Add Gen4 automotive device IDs (Kelvin Cao)
   - Declare state_names[] as static so it's not allocated and
     initialized for every call (Kelvin Cao)

  Host controller driver cleanups:
   - Use of_device_get_match_data(), not of_match_device(), when we only
     need the device data in altera, artpec6, cadence, designware-plat,
     dra7xx, keystone, kirin (Fan Fei)
   - Drop pointless of_device_get_match_data() cast in j721e (Bjorn
     Helgaas)
   - Drop redundant struct device * from j721e since struct cdns_pcie
     already has one (Bjorn Helgaas)
   - Rename driver structs to *_pcie in intel-gw, iproc, ls-gen4,
     mediatek-gen3, microchip, mt7621, rcar-gen2, tegra194, uniphier,
     xgene, xilinx, xilinx-cpm for consistency across drivers (Fan Fei)
   - Fix invalid address space conversions in hisi, spear13xx (Bjorn
     Helgaas)

  Miscellaneous:
   - Sort Intel Device IDs by value (Andy Shevchenko)
   - Change Capability offsets to hex to match spec (Baruch Siach)
   - Correct misspellings (Krzysztof Wilczyński)
   - Terminate statement with semicolon in pci_endpoint_test.c (Ming
     Wang)"

* tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (151 commits)
  PCI: mt7621: Allow COMPILE_TEST for all arches
  PCI: mt7621: Add missing MODULE_LICENSE()
  PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
  PCI: Let pcibios_root_bridge_prepare() access bridge->windows
  PCI: mt7621: Declare mt7621_pci_ops static
  PCI: brcmstb: Do not turn off WOL regulators on suspend
  PCI: brcmstb: Add control of subdevice voltage regulators
  PCI: brcmstb: Add mechanism to turn on subdev regulators
  PCI: brcmstb: Split brcm_pcie_setup() into two funcs
  dt-bindings: PCI: Add bindings for Brcmstb EP voltage regulators
  dt-bindings: PCI: Correct brcmstb interrupts, interrupt-map.
  PCI: brcmstb: Fix function return value handling
  PCI: brcmstb: Do not use __GENMASK
  PCI: brcmstb: Declare 'used' as bitmap, not unsigned long
  PCI: hv: Add arm64 Hyper-V vPCI support
  PCI: hv: Make the code arch neutral by adding arch specific interfaces
  PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors
  x86/PCI: Remove initialization of static variables to false
  PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum
  misc: pci_endpoint_test: Terminate statement with semicolon
  ...
 2022-01-16 08:08:11 +02:00
David E. Box 80b3485f7d PCI: Add #defines for accessing PCIe DVSEC fields 
Add #defines for accessing Vendor ID, Revision, Length, and ID offsets
in the Designated Vendor Specific Extended Capability (DVSEC). Defined
in PCIe r5.0, sec 7.9.6.

Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Link: https://lore.kernel.org/r/20211208015015.891275-2-david.e.box@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2021-12-22 13:56:19 +01:00
Baruch Siach fb82437fdd PCI: Change capability register offsets to hex 
Convert offsets of capability registers from decimal to hex.  This matches
the spec documents and is less error prone.

[bhelgaas: also convert other capabilities with offsets > 8]
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Link: https://lore.kernel.org/r/20210825160516.GA3576414@bjorn-Precision-5520/
Link: https://lore.kernel.org/r/aa067278adacbb59a675366052714081f4980f26.1637244780.git.baruch@tkos.co.il
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2021-12-15 15:33:02 -06:00
Pali Rohár 460275f124 PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros 
Define a macro PCI_EXP_DEVCTL_PAYLOAD_* for every possible Max Payload
Size in linux/pci_regs.h, in the same style as PCI_EXP_DEVCTL_READRQ_*.

Link: https://lore.kernel.org/r/20211005180952.6812-2-kabel@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
 2021-10-07 14:23:31 +01:00
Linus Torvalds 489e9fea66 Merge tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 
Pull PCI updates from Bjorn Helgaas:
 "Enumeration:
   - Decode PCIe 64 GT/s link speed (Gustavo Pimentel)
   - Remove unused HAVE_PCI_SET_MWI (Heiner Kallweit)
   - Reduce pci_set_cacheline_size() message to debug level (Heiner
     Kallweit)
   - Fix pci_slot_release() NULL pointer dereference (Jubin Zhong)
   - Unify ECAM constants in native PCI Express drivers (Krzysztof
     Wilczyński)
   - Return u8 from pci_find_capability() and similar (Puranjay Mohan)
   - Return u16 from pci_find_ext_capability() and similar (Bjorn
     Helgaas)
   - Fix ACPI companion lookup for device 0 on the root bus (Rafael J.
     Wysocki)

  Resource management:
   - Keep both device and resource name for config space remaps
     (Alexander Lobakin)
   - Bounds-check command-line resource alignment requests (Bjorn
     Helgaas)
   - Fix overflow in command-line resource alignment requests (Colin Ian
     King)

  Driver binding:
   - Avoid duplicate IDs in driver dynamic IDs list (Zhenzhong Duan)

  Power management:
   - Save/restore Precision Time Measurement Capability for
     suspend/resume (David E. Box)
   - Disable PTM during suspend to save power (David E. Box)
   - Add sysfs attribute for device power state (Maximilian Luz)
   - Rename pci_wakeup_bus() to pci_resume_bus() (Mika Westerberg)
   - Do not generate wakeup event when runtime resuming device (Mika
     Westerberg)
   - Save/restore ASPM L1SS Capability for suspend/resume (Vidya Sagar)

  Virtualization:
   - Mark AMD Raven iGPU ATS as broken in some platforms (Alex Deucher)
   - Add function 1 DMA alias quirk for Marvell 9215 SATA controller
     (Bjorn Helgaas)

  MSI:
   - Disable MSI for Pericom PCIe-USB adapter (Andy Shevchenko)
   - Improve warnings for 32-bit-limited MSI support (Vidya Sagar)

  Error handling:
   - Cache RCEC EA Capability offset in pci_init_capabilities() (Sean V
     Kelley)
   - Rename reset_link() to reset_subordinates() (Sean V Kelley)
   - Write AER Capability only when we control it (Sean V Kelley)
   - Clear AER status only when we control AER (Sean V Kelley)
   - Bind RCEC devices to the Root Port driver (Qiuxu Zhuo)
   - Recover from RCiEP AER errors (Qiuxu Zhuo)
   - Recover from RCEC AER errors (Sean V Kelley)
   - Add pcie_link_rcec() to associate RCiEPs (Sean V Kelley)
   - Add pcie_walk_rcec() to RCEC AER handling (Sean V Kelley)
   - Add pcie_walk_rcec() to RCEC PME handling (Sean V Kelley)
   - Add RCEC AER error injection support (Qiuxu Zhuo)

  Broadcom iProc PCIe controller driver:
   - Fix out-of-bound array accesses (Bharat Gooty)
   - Invalidate correct PAXB inbound windows (Roman Bacik)
   - Enhance PCIe Link information display (Srinath Mannam)

  Cadence PCIe controller driver:
   - Make "cdns,max-outbound-regions" property optional (Kishon Vijay
     Abraham I)

  Intel VMD host bridge driver:
   - Offset client MSI-X vectors (Jon Derrick)
   - Update type of __iomem pointers (Krzysztof Wilczyński)

  NVIDIA Tegra PCIe controller driver:
   - Move "dbi" accesses to post common DWC initialization (Vidya Sagar)
   - Read "dbi" base address to program in application logic (Vidya
     Sagar)
   - Fix ASPM-L1SS advertisement disable code (Vidya Sagar)
   - Set DesignWare IP version (Vidya Sagar)
   - Continue unconfig sequence even if parts fail (Vidya Sagar)
   - Check return value of tegra_pcie_init_controller() (Vidya Sagar)
   - Disable LTSSM during L2 entry (Vidya Sagar)

  Qualcomm PCIe controller driver:
   - Document PCIe bindings for SM8250 SoC (Manivannan Sadhasivam)
   - Add SM8250 SoC support (Manivannan Sadhasivam)
   - Add support for configuring BDF to SID mapping for SM8250
     (Manivannan Sadhasivam)

  Renesas R-Car PCIe controller driver:
   - rcar: Drop unused members from struct rcar_pcie_host (Lad
     Prabhakar)
   - PCI: rcar-pci-host: Document r8a774e1 bindings (Lad Prabhakar)
   - PCI: rcar-pci-host: Convert bindings to json-schema (Yoshihiro
     Shimoda)
   - PCI: rcar-pci-host: Document r8a77965 bindings (Yoshihiro Shimoda)

  Samsung Exynos PCIe controller driver:
   - Rework driver to support Exynos5433 PCIe PHY (Jaehoon Chung)
   - Rework driver to support Exynos5433 variant (Jaehoon Chung)
   - Drop samsung,exynos5440-pcie binding (Marek Szyprowski)
   - Add the samsung,exynos-pcie binding (Marek Szyprowski)
   - Add the samsung,exynos-pcie-phy binding (Marek Szyprowski)

  Synopsys DesignWare PCIe controller driver:
   - Support multiple ATU memory regions (Rob Herring)
   - Move intel-gw ATU offset out of driver match data (Rob Herring)
   - Move "dbi", "dbi2", and "addr_space" resource setup into common
     code (Rob Herring)
   - Remove intel-gw unneeded function wrappers (Rob Herring)
   - Ensure all outbound ATU windows are reset (Rob Herring)
   - Use the common MSI irq_chip in dra7xx (Rob Herring)
   - Drop the .set_num_vectors() host op (Rob Herring)
   - Move MSI interrupt setup into DWC common code (Rob Herring)
   - Rework MSI initialization (Rob Herring)
   - Move link handling into common code (Rob Herring)
   - Move dw_pcie_msi_init() into core (Rob Herring)
   - Move dw_pcie_setup_rc() to DWC common code (Rob Herring)
   - Remove unnecessary wrappers around dw_pcie_host_init() (Rob
     Herring)
   - Drop keystone duplicated 'num-viewport'" (Rob Herring)
   - Move inbound and outbound windows to common struct (Rob Herring)
   - Detect number of iATU windows (Rob Herring)
   - Warn if non-prefetchable memory aperture size is > 32-bit (Vidya
     Sagar)
   - Add support to program ATU for >4GB memory (Vidya Sagar)
   - Set 32-bit DMA mask for MSI target address allocation (Vidya Sagar)

  TI J721E PCIe driver:
   - Fix "ti,syscon-pcie-ctrl" to take argument (Kishon Vijay Abraham I)
   - Add host mode dt-bindings for TI's J7200 SoC (Kishon Vijay Abraham
     I)
   - Add EP mode dt-bindings for TI's J7200 SoC (Kishon Vijay Abraham I)
   - Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
     (Kishon Vijay Abraham I)

  TI Keystone PCIe controller driver:
   - Enable compile-testing on !ARM (Alex Dewar)"

* tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (100 commits)
  PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
  PCI/ACPI: Fix companion lookup for device 0 on the root bus
  PCI: Keep both device and resource name for config space remaps
  PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
  PCI: vmd: Update type of the __iomem pointers
  PCI: iproc: Convert to use the new ECAM constants
  PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
  PCI: Unify ECAM constants in native PCI Express drivers
  PCI: Disable PTM during suspend to save power
  PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
  PCI: Mark AMD Raven iGPU ATS as broken in some platforms
  PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
  dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
  dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
  PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
  PCI: Reduce pci_set_cacheline_size() message to debug level
  PCI: Remove unused HAVE_PCI_SET_MWI
  PCI: qcom: Add SM8250 SoC support
  ...
 2020-12-15 16:49:59 -08:00
Bjorn Helgaas 6a94785fb9 Merge branch 'pci/err' 
- Stop writing AER Capability when we don't own it (Sean V Kelley)

- Bind RCEC devices to the Port driver (Qiuxu Zhuo)

- Cache the RCEC RA Capability offset (Sean V Kelley)

- Add pci_walk_bridge() (Sean V Kelley)

- Clear AER status only when we control AER (Sean V Kelley)

- Recover from RCEC AER errors (Sean V Kelley)

- Add pcie_link_rcec() to associate RCiEPs with RCECs (Sean V Kelley)

- Recover from RCiEP AER errors (Sean V Kelley)

- Add pcie_walk_rcec() for RCEC AER handling (Sean V Kelley)

- Add pcie_walk_rcec() for RCEC PME handling (Sean V Kelley)

- Add RCEC AER error injection support (Qiuxu Zhuo)

* pci/err:
  PCI/AER: Add RCEC AER error injection support
  PCI/PME: Add pcie_walk_rcec() to RCEC PME handling
  PCI/AER: Add pcie_walk_rcec() to RCEC AER handling
  PCI/ERR: Recover from RCiEP AER errors
  PCI/ERR: Add pcie_link_rcec() to associate RCiEPs
  PCI/ERR: Recover from RCEC AER errors
  PCI/ERR: Clear AER status only when we control AER
  PCI/ERR: Add pci_walk_bridge() to pcie_do_recovery()
  PCI/ERR: Avoid negated conditional for clarity
  PCI/ERR: Use "bridge" for clarity in pcie_do_recovery()
  PCI/ERR: Simplify by computing pci_pcie_type() once
  PCI/ERR: Simplify by using pci_upstream_bridge()
  PCI/ERR: Rename reset_link() to reset_subordinates()
  PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities()
  PCI/ERR: Bind RCEC devices to the Root Port driver
  PCI/AER: Write AER Capability only when we control it
 2020-12-15 15:11:06 -06:00
Qiuxu Zhuo c9d659b607 PCI/ERR: Bind RCEC devices to the Root Port driver 
If a Root Complex Integrated Endpoint (RCiEP) is implemented, it may signal
errors through a Root Complex Event Collector (RCEC).  Each RCiEP must be
associated with no more than one RCEC.

For an RCEC (which is technically not a Bridge), error messages "received"
from associated RCiEPs must be enabled for "transmission" in order to cause
a System Error via the Root Control register or (when the Advanced Error
Reporting Capability is present) reporting via the Root Error Command
register and logging in the Root Error Status register and Error Source
Identification register.

Given the commonality with Root Ports and the need to also support AER and
PME services for RCECs, extend the Root Port driver to support RCEC devices
by adding the RCEC Class ID to the driver structure.

Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-3-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
 2020-12-04 11:18:42 -06:00
Gustavo Pimentel 341917490d PCI: Decode PCIe 64 GT/s link speed 
PCIe r6.0, sec 7.5.3.18, defines a new 64.0 GT/s bit in the Supported Link
Speeds Vector of Link Capabilities 2.

This patch does not affect the speed of the link, which should be
negotiated automatically by the hardware; it only adds decoding when
showing the speed to the user.

Decode this new speed.  Previously, reading the speed of a link operating
at this speed showed "Unknown speed" instead of "64.0 GT/s".

Link: https://lore.kernel.org/r/aaaab33fe18975e123a84aebce2adb85f44e2bbe.1605739760.git.gustavo.pimentel@synopsys.com
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
 2020-11-20 12:35:27 -06:00
David E. Box 1dc2da5cd5 PCI: Add defines for Designated Vendor-Specific Extended Capability 
Add PCIe Designated Vendor-Specific Extended Capability (DVSEC) and defines
for the header offsets. Defined in PCIe r5.0, sec 7.9.6.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
 2020-11-04 11:13:35 +00:00
Bjorn Helgaas 924bb1f9b0 Merge branch 'remotes/lorenzo/pci/dwc' 
- Fix designware-ep Header Type check (Hou Zhiqiang)

- Use DBI accessors instead of own config accessors (Rob Herring)

- Allow overriding bridge pci_ops (Rob Herring)

- Allow root and child buses to have different pci_ops (Rob Herring)

- Add default dwc pci_ops.map_bus (Rob Herring)

- Use pci_ops for root config space accessors in al, exynos, histb,
  keystone, kirin, meson, tegra (Rob Herring)

- Remove dwc own/other config accessor ops (Rob Herring)

- Use generic config accessors in dwc (Rob Herring)

- Also call .add_bus() callback for root bus (Rob Herring)

- Convert keystone .scan_bus() callback to use pci_ops.add_bus (Rob
  Herring)

- Convert dwc to use pci_host_probe() (Rob Herring)

- Remove dwc root_bus pointer (Rob Herring)

- Remove storing of PCI resources in dwc-specific structs (Rob Herring)

- Simplify config space handling (Rob Herring)

- Drop keystone duplicated DT num-viewport handling (Rob Herring)

- Check CONFIG_PCI_MSI in dw_pcie_msi_init() instead of duplicating it in
  all the drivers (Rob Herring)

- Remove imx6 duplicate PCIE_LINK_WIDTH_SPEED_CONTROL definition (Rob
  Herring)

- Add dwc num_lanes for use when it's lacking from DT (Rob Herring)

- Ensure "Fast Link Mode" simulation environment setting is cleared (Rob
  Herring)

- Drop meson duplicate number of lanes setup (Rob Herring)

- Drop meson unnecessary RC config space init (Rob Herring)

- Rework meson config and dwc port logic register accesses (Rob Herring)

- Use common PCI register definitions in imx6 and qcom (Rob Herring)

- Search for DesignWare PCIe Capability instead of hard-coding its location
  (Rob Herring)

- Use common DesignWare register definitions in tegra (Rob Herring)

- Drop keystone unused DBI2 code (Rob Herring)

- Make dwc ATU accessors private (Rob Herring)

- Centralize link gen setting in dwc (Rob Herring)

- Set PORT_LINK_DLL_LINK_EN in common dwc setup code (Rob Herring)

- Drop intel-gw unnecessary DT 'device_type' checking (Rob Herring)

- Move intel-gw PCI_CAP_ID_EXP discovery to the single place it's used (Rob
  Herring)

- Drop intel-gw unused max_width (Rob Herring)

- Move N_FTS (fast training sequence) setup to common dwc setup (Rob
  Herring)

- Convert spear13xx, tegra194 to use DBI accessors (Rob Herring)

- Add multiple PFs support for DWC (Xiaowei Bao)

- Add MSI-X doorbell mode for endpoint mode (Xiaowei Bao)

- Update MSI/MSI-X capability management for endpoints (Xiaowei Bao)

- Add layerscape ls1088a and ls2088a compatible strings (Xiaowei Bao)

- Update layerscape MSI/MSI-X management (Xiaowei Bao)

- Use doorbell to support MSI-X on layerscape (Xiaowei Bao)

- Add layerscape endpoint mode support for ls1088a and ls2088a (Xiaowei
  Bao)

- Add layerscape ls1088a node to DT (Xiaowei Bao)

- Add Freescale/Layerscape ls1088a to endpoint test (Xiaowei Bao)

- Add endpoint test driver data for Layerscape PCIe controllers (Hou
  Zhiqiang)

- Fix 'cast truncates bits from constant value' warning (Gustavo Pimentel)

- Add uniphier iATU register description (Kunihiko Hayashi)

- Add common iATU register support (Kunihiko Hayashi)

- Remove keystone iATU register mapping in favor of generic dwc support
  (Kunihiko Hayashi)

- Skip PCIE_MSI_INTR0* programming if MSI is disabled (Jisheng Zhang)

- Fix MSI page leakage in suspend/resume (Jisheng Zhang)

- Check whether link is up before attempting config access (best-effort fix
  even though it's racy) (Hou Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()
  PCI: dwc: Fix MSI page leakage in suspend/resume
  PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled
  PCI: keystone: Remove iATU register mapping
  PCI: dwc: Add common iATU register support
  dt-bindings: PCI: uniphier-ep: Add iATU register description
  dt-bindings: PCI: uniphier: Add iATU register description
  PCI: dwc: Fix 'cast truncates bits from constant value'
  misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers
  misc: pci_endpoint_test: Add LS1088a in pci_device_id table
  PCI: layerscape: Add EP mode support for ls1088a and ls2088a
  PCI: layerscape: Modify the MSIX to the doorbell mode
  PCI: layerscape: Modify the way of getting capability with different PEX
  PCI: layerscape: Fix some format issue of the code
  dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a
  PCI: designware-ep: Modify MSI and MSIX CAP way of finding
  PCI: designware-ep: Move the function of getting MSI capability forward
  PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode
  PCI: designware-ep: Add multiple PFs support for DWC
  PCI: dwc: Use DBI accessors
  PCI: dwc: Move N_FTS setup to common setup
  PCI: dwc/intel-gw: Drop unused max_width
  PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()
  PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property
  PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code
  PCI: dwc: Centralize link gen setting
  PCI: dwc: Make ATU accessors private
  PCI: dwc: Remove read_dbi2 code
  PCI: dwc/tegra: Use common Designware port logic register definitions
  PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset
  PCI: dwc/qcom: Use common PCI register definitions
  PCI: dwc/imx6: Use common PCI register definitions
  PCI: dwc/meson: Rework PCI config and DW port logic register accesses
  PCI: dwc/meson: Drop unnecessary RC config space initialization
  PCI: dwc/meson: Drop the duplicate number of lanes setup
  PCI: dwc: Ensure FAST_LINK_MODE is cleared
  PCI: dwc: Add a 'num_lanes' field to struct dw_pcie
  PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL
  PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()
  PCI: dwc/keystone: Drop duplicated 'num-viewport'
  PCI: dwc: Simplify config space handling
  PCI: dwc: Remove storing of PCI resources
  PCI: dwc: Remove root_bus pointer
  PCI: dwc: Convert to use pci_host_probe()
  PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus
  PCI: Also call .add_bus() callback for root bus
  PCI: dwc: Use generic config accessors
  PCI: dwc: Remove dwc specific config accessor ops
  PCI: dwc: histb: Use pci_ops for root config space accessors
  PCI: dwc: exynos: Use pci_ops for root config space accessors
  PCI: dwc: kirin: Use pci_ops for root config space accessors
  PCI: dwc: meson: Use pci_ops for root config space accessors
  PCI: dwc: tegra: Use pci_ops for root config space accessors
  PCI: dwc: keystone: Use pci_ops for config space accessors
  PCI: dwc: al: Use pci_ops for child config space accessors
  PCI: dwc: Add a default pci_ops.map_bus for root port
  PCI: dwc: Allow overriding bridge pci_ops
  PCI: dwc: Use DBI accessors instead of own config accessors
  PCI: Allow root and child buses to have different pci_ops
  PCI: designware-ep: Fix the Header Type check
 2020-10-21 09:58:39 -05:00
Bjorn Helgaas 0d2493ab08 Merge branch 'pci/pm' 
- Remove unused pcibios_pm_ops (Vaibhav Gupta)

- Rename pci_dev.d3_delay to d3hot_delay (Krzysztof Wilczyński)

- Apply D2 transition delay as microseconds, not milliseconds (Bjorn
  Helgaas)

* pci/pm:
  PCI/PM: Revert "PCI/PM: Apply D2 delay as milliseconds, not microseconds"
  PCI/PM: Remove unused PCI_PM_BUS_WAIT
  PCI/PM: Rename pci_dev.d3_delay to d3hot_delay
  PCI/PM: Remove unused pcibios_pm_ops
 2020-10-21 09:58:35 -05:00
Saheed O. Bolarinwa df8f10587d PCI/ASPM: Remove struct pcie_link_state.l1ss 
Previously we computed L1.2 parameters in the enumeration path, saved them
in struct pcie_link_state.l1ss, and programmed them into the devices
whenever we enabled or disabled L1.2 on the link.  But these parameters are
constant and don't need to be updated when enabling/disabling L1.2.

Compute and program the L1.2 parameters once during enumeration and remove
the struct pcie_link_state.l1ss member.  No functional change intended.

[bhelgaas: rework to program L1.2 parameters during enumeration]
Link: https://lore.kernel.org/r/20201015193039.12585-13-helgaas@kernel.org
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2020-10-16 11:21:19 -05:00
Saheed O. Bolarinwa c6e5f02b52 PCI/ASPM: Remove struct aspm_register_info.support 
Previously we stored the "ASPM Support" field from the Link Capabilities
register in the struct aspm_register_info.

Read the Link Capabilities directly when needed and remove it from the
struct aspm_register_info.  No functional change intended.

[bhelgaas: remove pci_dev cached copy since LNKCAP isn't truly read-only,
add PCI_EXP_LNKCAP_ASPM_L0S & PCI_EXP_LNKCAP_ASPM_L1, check them directly
instead of adding aspm_support()]
Link: https://lore.kernel.org/r/20201015193039.12585-5-helgaas@kernel.org
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2020-10-16 11:20:53 -05:00
Krzysztof Wilczyński 3789af9a13 PCI/PM: Rename pci_dev.d3_delay to d3hot_delay 
PCI devices support two variants of the D3 power state: D3hot (main power
present) D3cold (main power removed).  Previously struct pci_dev contained:

  unsigned int    d3_delay;       /* D3->D0 transition time in ms */
  unsigned int    d3cold_delay;   /* D3cold->D0 transition time in ms */

"d3_delay" refers specifically to the D3hot state.  Rename it to
"d3hot_delay" to avoid ambiguity and align with the ACPI "_DSM for
Specifying Device Readiness Durations" in the PCI Firmware spec r3.2,
sec 4.6.9.

There is no change to the functionality.

Link: https://lore.kernel.org/r/20200730210848.1578826-1-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2020-09-29 14:21:50 -05:00
Hou Zhiqiang 16270a9235 PCI: designware-ep: Fix the Header Type check 
The current check will result in the multiple function device
fails to initialize. So fix the check by masking out the
multiple function bit.

Link: https://lore.kernel.org/r/20200818092746.24366-1-Zhiqiang.Hou@nxp.com
Fixes: 0b24134f78 ("PCI: dwc: Add validation that PCIe core is set to correct mode")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
 2020-09-07 10:25:22 +01:00
Alexandru Gagniuc 202853595e PCI: pciehp: Disable in-band presence detect when possible 
The presence detect state (PDS) is normally a logical OR of in-band and
out-of-band (OOB) presence detect.  As of PCIe 4.0, there is the option to
disable in-band presence so that the PDS bit always reflects the state of
the out-of-band presence.

The recommendation of the PCIe spec is to disable in-band presence whenever
supported (PCIe r5.0, appendix I implementation note):

  Due to architectural issues, the in-band (Physical-Layer-based) portion
  of the PD mechanism is deprecated for use with async hot-plug. One issue
  is that in-band PD as architected does not detect adapter removal during
  certain LTSSM states, notably the L1 and Disabled States.  Another issue
  is that when both in-band and OOB PD are being used together, the
  Presence Detect State bit and its associated interrupt mechanism always
  reflect the logical OR of the inband and OOB PD states, and with some
  hot-plug hardware configurations, it is important for software to detect
  and respond to in-band and OOB PD events independently.  If OOB PD is
  being used and the associated DSP supports In-Band PD Disable, it is
  recommended that the In-Band PD Disable bit be Set, and the Presence
  Detect State bit and its associated interrupt mechanism be used
  exclusively for OOB PD.  As a substitute for in-band PD with async
  hot-plug, the reference model uses either the DPC or the DLL Link Active
  mechanism.

Link: https://lore.kernel.org/r/20191025190047.38130-2-stuart.w.hayes@gmail.com
[bhelgaas: move PCI_EXP_SLTCAP2 read earlier & print PCI_EXP_SLTCAP2_IBPD
value (suggested by Lukas)]
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
 2020-02-20 22:44:30 -06:00
Dilip Kota ed22aaaede PCI: dwc: intel: PCIe RC controller driver 
Add support to PCIe RC controller on Intel Gateway SoCs.
PCIe controller is based of Synopsys DesignWare PCIe core.

Intel PCIe driver requires Upconfigure support, Fast Training
Sequence and link speed configurations. So adding the respective
helper functions in the PCIe DesignWare framework.
It also programs hardware autonomous speed during speed
configuration so defining it in pci_regs.h.

Also, mark Intel PCIe driver depends on MSI IRQ Domain
as Synopsys DesignWare framework depends on the
PCI_MSI_IRQ_DOMAIN.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
 2020-01-09 11:57:18 +00:00
Bjorn Helgaas 774800cb09 Merge branch 'pci/resource' 
- Protect pci_reassign_bridge_resources() against concurrent
    addition/removal (Benjamin Herrenschmidt)

  - Fix bridge dma_ranges resource list cleanup (Rob Herring)

  - Add PCI_STD_NUM_BARS for the number of standard BARs (Denis Efremov)

  - Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters to control the
    MMIO and prefetchable MMIO window sizes of hotplug bridges
    independently (Nicholas Johnson)

  - Fix MMIO/MMIO_PREF window assignment that assigned more space than
    desired (Nicholas Johnson)

  - Only enforce bus numbers from bridge EA if the bridge has EA devices
    downstream (Subbaraya Sundeep)

* pci/resource:
  PCI: Do not use bus number zero from EA capability
  PCI: Avoid double hpmemsize MMIO window assignment
  PCI: Add "pci=hpmmiosize" and "pci=hpmmioprefsize" parameters
  PCI: Add PCI_STD_NUM_BARS for the number of standard BARs
  PCI: Fix missing bridge dma_ranges resource list cleanup
  PCI: Protect pci_reassign_bridge_resources() against concurrent addition/removal
 2019-11-28 08:54:36 -06:00
Bjorn Helgaas bbdb2f5ecd PCI: Add #defines for Enter Compliance, Transmit Margin 
Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.

Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2019-11-21 07:52:34 -06:00
Denis Efremov c9c13ba428 PCI: Add PCI_STD_NUM_BARS for the number of standard BARs 
Code that iterates over all standard PCI BARs typically uses
PCI_STD_RESOURCE_END.  However, that requires the unusual test
"i <= PCI_STD_RESOURCE_END" rather than something the typical
"i < PCI_STD_NUM_BARS".

Add a definition for PCI_STD_NUM_BARS and change loops to use the more
idiomatic C style to help avoid fencepost errors.

Link: https://lore.kernel.org/r/20190927234026.23342-1-efremov@linux.com
Link: https://lore.kernel.org/r/20190927234308.23935-1-efremov@linux.com
Link: https://lore.kernel.org/r/20190916204158.6889-3-efremov@linux.com
Signed-off-by: Denis Efremov <efremov@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Sebastian Ott <sebott@linux.ibm.com>			# arch/s390/
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>	# video/fbdev/
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>	# pci/controller/dwc/
Acked-by: Jack Wang <jinpu.wang@cloud.ionos.com>		# scsi/pm8001/
Acked-by: Martin K. Petersen <martin.petersen@oracle.com>	# scsi/pm8001/
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>			# memstick/
 2019-10-14 10:22:26 -05:00
Bjorn Helgaas 3efa7f1feb Merge branch 'lorenzo/pci/tegra' 
- Fix Tegra OF node reference leak (Nishka Dasgupta)

  - Add #defines for PCIe Data Link Feature and Physical Layer 16.0 GT/s
    features (Vidya Sagar)

  - Disable MSI for Tegra Root Ports since they don't support using MSI for
    all Root Port events (Vidya Sagar)

  - Group DesignWare write-protected register writes together (Vidya Sagar)

  - Move DesignWare capability search interfaces so they can be used by
    both host and endpoint drivers (Vidya Sagar)

  - Add DesignWare extended capability search interfaces (Vidya Sagar)

  - Export dw_pcie_wait_for_link() so drivers can be modules (Vidya Sagar)

  - Add "snps,enable-cdm-check" DT binding for Configuration Dependent
    Module (CDM) register checking (Vidya Sagar)

  - Add DesignWare support for "snps,enable-cdm-check" CDM checking (Vidya
    Sagar)

  - Add "supports-clkreq" DT binding for host drivers to decide whether to
    advertise low power features (Vidya Sagar)

  - Add DT binding for Tegra194 (Vidya Sagar)

  - Add DT binding for Tegra194 P2U (PIPE to UPHY) block (Vidya Sagar)

  - Add support for Tegra194 P2U (PIPE to UPHY) (Vidya Sagar)

  - Add support for Tegra194 host controller (Vidya Sagar)

  - Add Tegra support for sideband PERST# and CLKREQ# for C5 (Vidya Sagar)

  - Add Tegra support for slot regulators for p2972-0000 platform (Vidya
    Sagar)

* lorenzo/pci/tegra:
  arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
  arm64: tegra: Add configuration for PCIe C5 sideband signals
  PCI: tegra: Add support to enable slot regulators
  PCI: tegra: Add support to configure sideband pins
  dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
  dt-bindings: PCI: tegra: Add sideband pins configuration entries
  PCI: tegra: Add Tegra194 PCIe support
  phy: tegra: Add PCIe PIPE2UPHY support
  dt-bindings: PHY: P2U: Add Tegra194 P2U block
  dt-bindings: PCI: tegra: Add device tree support for Tegra194
  dt-bindings: Add PCIe supports-clkreq property
  PCI: dwc: Add support to enable CDM register check
  dt-bindings: PCI: designware: Add binding for CDM register check
  PCI: dwc: Export dw_pcie_wait_for_link() API
  PCI: dwc: Add extended configuration space capability search API
  PCI: dwc: Move config space capability search API
  PCI: dwc: Group DBI registers writes requiring unlocking
  PCI: Disable MSI for Tegra root ports
  PCI: Add #defines for some of PCIe spec r4.0 features
  PCI: tegra: Fix OF node reference leak
 2019-09-23 16:10:28 -05:00
Denis Efremov 106feb2fdc PCI: pciehp: Remove pciehp_set_attention_status() 
Remove pciehp_set_attention_status() and use pciehp_set_indicators()
instead, since the code is mostly the same.

Link: https://lore.kernel.org/r/20190903111021.1559-4-efremov@linux.com
Signed-off-by: Denis Efremov <efremov@linux.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
 2019-09-05 15:44:08 -05:00
Vidya Sagar 448d5a5575 PCI: Add #defines for some of PCIe spec r4.0 features 
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and
sec 7.7.5 for Physical Layer 16.0 GT/s.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
 2019-08-13 15:41:46 +01:00
Gustavo Pimentel de76cda215 PCI: Decode PCIe 32 GT/s link speed 
PCIe r5.0, sec 7.5.3.18, defines a new 32.0 GT/s bit in the Supported Link
Speeds Vector of Link Capabilities 2.  Decode this new speed.  This does
not affect the speed of the link, which should be negotiated automatically
by the hardware; it only adds decoding when showing the speed to the user.

Previously, reading the speed of a link operating at this speed showed
"Unknown speed" instead of "32.0 GT/s".

Link: https://lore.kernel.org/lkml/92365e3caf0fc559f9ab14bcd053bfc92d4f661c.1559664969.git.gustavo.pimentel@synopsys.com
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
 2019-06-13 16:49:45 -05:00
Bjorn Helgaas c7a1c2bbb6 Merge branch 'pci/trivial' 
- Cleanup PCI register definitions, typos, etc (Bjorn Helgaas)

  - Remove unnecessary use of user-space types in CPER (Bjorn Helgaas)

  - Cleanup setup-bus.c comments & whitespace (Nicholas Johnson)

* pci/trivial:
  PCI: Cleanup setup-bus.c comments and whitespace
  CPER: Remove unnecessary use of user-space types
  CPER: Add UEFI spec references
  PCI: Fix comment typos
  PCI: Cleanup register definition width and whitespace

# Conflicts:
#	drivers/pci/pci.c
#	drivers/pci/setup-bus.c
 2019-05-13 18:34:48 -05:00