Linus Torvalds
|
3604a7f568
|
Merge tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu:
"API:
- Feed untrusted RNGs into /dev/random
- Allow HWRNG sleeping to be more interruptible
- Create lib/utils module
- Setting private keys no longer required for akcipher
- Remove tcrypt mode=1000
- Reorganised Kconfig entries
Algorithms:
- Load x86/sha512 based on CPU features
- Add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher
Drivers:
- Add HACE crypto driver aspeed"
* tag 'v6.1-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (124 commits)
crypto: aspeed - Remove redundant dev_err call
crypto: scatterwalk - Remove unused inline function scatterwalk_aligned()
crypto: aead - Remove unused inline functions from aead
crypto: bcm - Simplify obtain the name for cipher
crypto: marvell/octeontx - use sysfs_emit() to instead of scnprintf()
hwrng: core - start hwrng kthread also for untrusted sources
crypto: zip - remove the unneeded result variable
crypto: qat - add limit to linked list parsing
crypto: octeontx2 - Remove the unneeded result variable
crypto: ccp - Remove the unneeded result variable
crypto: aspeed - Fix check for platform_get_irq() errors
crypto: virtio - fix memory-leak
crypto: cavium - prevent integer overflow loading firmware
crypto: marvell/octeontx - prevent integer overflows
crypto: aspeed - fix build error when only CRYPTO_DEV_ASPEED is enabled
crypto: hisilicon/qm - fix the qos value initialization
crypto: sun4i-ss - use DEFINE_SHOW_ATTRIBUTE to simplify sun4i_ss_debugfs
crypto: tcrypt - add async speed test for aria cipher
crypto: aria-avx - add AES-NI/AVX/x86_64/GFNI assembler implementation of aria cipher
crypto: aria - prepare generic module for optimized implementations
...
|
2022-10-10 13:04:25 -07:00 |
|
Stephen Boyd
|
b7f257ceb3
|
Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' into clk-next
- More devm helpers for fixed rate registration
- Add Spreadtrum UMS512 SoC clk support
- Various PXA168 clk driver fixes
* clk-fixed-rate:
clk: fixed-rate: add devm_clk_hw_register_fixed_rate
clk: asm9260: use parent index to link the reference clock
* clk-spreadtrum:
clk: sprd: Add clocks support for UMS512
* clk-pxa:
clk: pxa: add a check for the return value of kzalloc()
clk: mmp: pxa168: control shared SDH bits with separate clock
dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks
clk: mmp: pxa168: add clocks for SDH2 and SDH3
dt-bindings: marvell,pxa168: add clock id for SDH3
clk: mmp: pxa168: fix GPIO clock enable bits
clk: mmp: pxa168: add muxes for more peripherals
clk: mmp: pxa168: fix incorrect parent clocks
clk: mmp: pxa168: fix const-correctness
clk: mmp: pxa168: add new clocks for peripherals
dt-bindings: marvell,pxa168: add clock ids for additional dividers
clk: mmp: pxa168: fix incorrect dividers
clk: mmp: pxa168: add additional register defines
* clk-ti:
clk: davinci: cfgchip: Use dev_err_probe() helper
clk: davinci: pll: fix spelling typo in comment
MAINTAINERS: add header file to TI DAVINCI SERIES CLOCK DRIVER
|
2022-10-04 10:54:14 -07:00 |
|
Stephen Boyd
|
26bebbfed5
|
Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner' and 'clk-imx' into clk-next
* clk-rockchip:
dt-bindings: clock: rockchip: change SPDX-License-Identifier
dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML
clk: rockchip: Add clock controller support for RV1126 SoC
dt-bindings: clock: rockchip: Document RV1126 CRU
clk: rockchip: Add dt-binding header for RV1126
clk: rockchip: Add MUXTBL variant
* clk-renesas:
clk: renesas: r8a779g0: Add EtherAVB clocks
clk: renesas: r8a779g0: Add PFC/GPIO clocks
clk: renesas: r8a779g0: Add I2C clocks
clk: renesas: r8a779g0: Add watchdog clock
dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
clk: renesas: r8a779f0: Add MSIOF clocks
clk: renesas: r9a09g011: Add IIC clock and reset entries
clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info
clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
clk: renesas: r8a779f0: Add CMT clocks
clk: renesas: r8a779f0: Add SDH0 clock
* clk-microchip:
clk: at91: sama5d2: Add Generic Clocks for UART/USART
clk: microchip: add PolarFire SoC fabric clock support
dt-bindings: clk: add PolarFire SoC fabric clock ids
dt-bindings: clk: document PolarFire SoC fabric clocks
dt-bindings: clk: rename mpfs-clkcfg binding
clk: microchip: mpfs: update module authorship & licencing
clk: microchip: mpfs: convert periph_clk to clk_gate
clk: microchip: mpfs: convert cfg_clk to clk_divider
clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
clk: microchip: mpfs: simplify control reg access
clk: microchip: mpfs: move id & offset out of clock structs
clk: microchip: mpfs: add MSS pll's set & round rate
MAINTAINERS: add polarfire soc reset controller
reset: add polarfire soc reset support
clk: microchip: mpfs: add reset controller
dt-bindings: clk: microchip: mpfs: add reset controller support
clk: microchip: mpfs: make the rtc's ahb clock critical
clk: microchip: mpfs: fix clk_cfg array bounds violation
* clk-allwinner:
clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper
clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper
clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper
clk: sunxi-ng: d1: Limit PLL rates to stable ranges
* clk-imx:
clk: imx: scu: fix memleak on platform_device_add() fails
clk: imx93: add SAI IPG clk
clk: imx93: add MU1/2 clock
clk: imx93: switch to use new clk gate API
clk: imx: add i.MX93 clk gate
clk: imx: clk-composite-93: check white_list
clk: imx: clk-composite-93: check slice busy
dt-bindings: clock: imx93-clock: add more MU/SAI clocks
dt-bindings: clock: imx8mm: don't use multiple blank lines
clk: imx8mp: tune the order of enet_qos_root_clk
|
2022-10-04 10:54:02 -07:00 |
|
Stephen Boyd
|
a64b79c01c
|
Merge branches 'clk-samsung', 'clk-mtk', 'clk-rm', 'clk-ast' and 'clk-qcom' into clk-next
- Add resets for MediaTek MT8195 PCIe and USB
- Remove DaVinci DM644x and DM646x clk driver support
* clk-samsung:
clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
clk: samsung: exynos850: Implement CMU_MFCMSCL domain
clk: samsung: exynos850: Implement CMU_IS domain
clk: samsung: exynos850: Implement CMU_AUD domain
clk: samsung: exynos850: Style fixes
clk: samsung: exynosautov9: add fsys1 clock support
clk: samsung: exynosautov9: add fsys0 clock support
clk: samsung: exynosautov9: correct register offsets of peric0/c1
clk: samsung: exynosautov9: add missing gate clks for peric0/c1
dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
dt-bindings: clock: exynosautov9: add fsys1 clock definitions
dt-bindings: clock: exynosautov9: add fys0 clock definitions
clk: samsung: exynos7885: Add TREX clocks
clk: samsung: exynos7885: Implement CMU_FSYS domain
dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
clk: samsung: exynos-clkout: Use of_device_get_match_data()
* clk-mtk: (42 commits)
clk: mediatek: add driver for MT8365 SoC
clk: mediatek: Export required common code symbols
clk: mediatek: Provide mtk_devm_alloc_clk_data
dt-bindings: clock: mediatek: add bindings for MT8365 SoC
clk: mediatek: mt8192: deduplicate parent clock lists
clk: mediatek: Migrate remaining clk_unregister_*() to clk_hw_unregister_*()
clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup
clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel
clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent
clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier
clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux
clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes
clk: mediatek: mt8183: Add clk mux notifier for MFG mux
clk: mediatek: mux: add clk notifier functions
clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent
clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe
clk: mediatek: gate: Export mtk_clk_register_gates_with_dev
clk: mediatek: add VDOSYS1 clock
dt-bindings: clk: mediatek: Add MT8195 DPI clocks
...
* clk-rm:
clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x
* clk-ast:
clk: ast2600: BCLK comes from EPLL
* clk-qcom: (97 commits)
clk: qcom: gcc-sm6375: Ensure unsigned long type
clk: qcom: gcc-sm6375: Remove unused variables
clk: qcom: kpss-xcc: convert to parent data API
clk: introduce (devm_)hw_register_mux_parent_data_table API
clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: gcc-msm8939: use parent_hws where possible
dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml
clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs
clk: qcom: gcc-sc8280xp: use retention for USB power domains
clk: qcom: gdsc: add missing error handling
dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos
clk: qcom: Add global clock controller driver for SM6375
dt-bindings: clock: add SM6375 QCOM global clock bindings
clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit
clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs
clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc
clk: qcom: gdsc: Fix the handling of PWRSTS_RET support
clk: qcom: Add SC8280XP GPU clock controller
dt-bindings: clock: Add Qualcomm SC8280XP GPU binding
clk: qcom: smd: Add SM6375 clocks
...
|
2022-10-04 10:53:41 -07:00 |
|
Fabien Parent
|
c61978175a
|
dt-bindings: clock: mediatek: add bindings for MT8365 SoC
Add the clock bindings for the MediaTek MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Link: https://lore.kernel.org/r/20220822152652.3499972-2-msp@baylibre.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
2022-09-30 15:07:43 -07:00 |
|
Doug Brown
|
238e73edce
|
dt-bindings: marvell,pxa168: add clock ids for SDH AXI clocks
These are clocks shared by SDH0/1 and SDH2/3, respectively.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-12-doug@schmorgal.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
2022-09-30 13:34:07 -07:00 |
|
Doug Brown
|
ca41820b9d
|
dt-bindings: marvell,pxa168: add clock id for SDH3
There are four SDHC peripherals on the PXA168, but only three of them
were present in the DT bindings. This commit adds the fourth.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-10-doug@schmorgal.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
2022-09-30 13:34:06 -07:00 |
|
Doug Brown
|
260d2f347b
|
dt-bindings: marvell,pxa168: add clock ids for additional dividers
This adds a few new clocks divided from PLL1 and CLK32 that are
potentially used by a few peripherals with muxed clocks.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-4-doug@schmorgal.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
2022-09-30 13:34:06 -07:00 |
|
Konrad Dybcio
|
43398afc0b
|
dt-bindings: clock: add SM6375 QCOM global clock bindings
Add device tree bindings for global clock controller for SM6375 SoCs.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921001303.56151-2-konrad.dybcio@somainline.org
|
2022-09-27 22:25:57 -05:00 |
|
Bjorn Andersson
|
9f60eb3ec0
|
dt-bindings: clock: Add Qualcomm SC8280XP GPU binding
Add compatible for the Qualcomm SC8280XP GPU.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220926173025.4747-2-quic_bjorande@quicinc.com
|
2022-09-27 12:07:30 -05:00 |
|
Konrad Dybcio
|
65cfaf4efa
|
dt-bindings: clock: qcom: rpmcc: Add BIMC_FREQ_LOG
Add the missing definition for the aforementioned clock.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220921004458.151842-2-konrad.dybcio@somainline.org
|
2022-09-27 12:07:17 -05:00 |
|
Dmitry Baryshkov
|
a7edd29163
|
dt-bindings: clock: qcom: add bindings for dispcc on SM8450
Add device tree bindings for the display clock controller on Qualcomm
SM8450 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220908222850.3552050-2-dmitry.baryshkov@linaro.org
|
2022-09-26 22:17:14 -05:00 |
|
Adam Skladowski
|
38557c6fc0
|
dt-bindings: clock: add QCOM SM6115 display clock bindings
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM6115 SoC.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
[bjorn: Minor fix of binding description]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220911164635.182973-2-a39.skl@gmail.com
|
2022-09-26 22:17:13 -05:00 |
|
Christian Marangi
|
d7081998cc
|
dt-bindings: clock: add pcm reset for ipq806x lcc
Add pcm reset define for ipq806x lcc.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220724182329.9891-1-ansuelsmth@gmail.com
|
2022-09-26 11:18:56 -05:00 |
|
Pablo Sun
|
879b752b97
|
dt-bindings: clk: mediatek: Add MT8195 DPI clocks
Expand dt-bindings slot for VDOSYS1 of MT8195.
This clock is required by the DPI1 hardware
and is a downstream of the HDMI pixel clock.
Signed-off-by: Pablo Sun <pablo.sun@mediatek.com>
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220919-v1-1-4844816c9808@baylibre.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
|
2022-09-26 13:26:19 +08:00 |
|
AngeloGioacchino Del Regno
|
32ccd1ab09
|
dt-bindings: clock: Add MediaTek Helio X10 MT6795 clock bindings
Add the bindings for MT6795's clock controller.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220921091455.41327-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
|
2022-09-26 11:13:09 +08:00 |
|
Peng Fan
|
90e58072b9
|
dt-bindings: clock: imx93-clock: add more MU/SAI clocks
Add MU[1,2]_[A,B] clock entries.
Add SAI IPG clock entries.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220830033137.4149542-2-peng.fan@oss.nxp.com
|
2022-09-19 13:06:45 +03:00 |
|
Marcel Ziswiler
|
59dc69d7c3
|
dt-bindings: clock: imx8mm: don't use multiple blank lines
Avoid the following checkpatch warning:
include/dt-bindings/clock/imx8mm-clock.h:284: check: Please don't use
multiple blank lines
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220722215445.3548530-13-marcel@ziswiler.com
|
2022-09-19 13:05:12 +03:00 |
|
Jagan Teki
|
bc35a430df
|
clk: rockchip: Add dt-binding header for RV1126
Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20220915163947.1922183-3-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
2022-09-17 16:27:59 +02:00 |
|
Conor Dooley
|
b4b025246c
|
dt-bindings: clk: add PolarFire SoC fabric clock ids
Each Clock Conditioning Circuitry block contains 2 PLLs and 2 DLLs.
The PLLs have 4 outputs each and the DLLs 2. Add 16 new IDs covering
these clocks. For more information on the CCC hardware, see the
"PolarFire SoC FPGA Clocking Resources" document at the link below.
Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-4-conor.dooley@microchip.com
|
2022-09-14 10:57:07 +03:00 |
|
Stephan Gerhold
|
c40668048f
|
dt-bindings: clock: Add schema for MSM8909 GCC
The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks,
resets and power domains for the various hardware blocks in the SoC.
Add a DT schema to describe it, similar to other Qualcomm SoCs.
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-2-stephan.gerhold@kernkonzept.com
|
2022-09-13 22:07:25 -05:00 |
|
Richard Acayan
|
657e932665
|
dt-bindings: clock: gcc-sdm845: add sdm670 global clocks
The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most
of the new clocks, GDSCs, and resets already have reserved IDs but there
are some resources that don't. Add the new clock from Snapdragon 670 and
document the differences between the SoC parent clocks.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220914013922.198778-2-mailingradian@gmail.com
|
2022-09-13 21:20:33 -05:00 |
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Taniya Das
|
1c3f9df77a
|
dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280
Support external mclk to interface external MI2S clocks for SC7280.
Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-5-git-send-email-quic_c_skakit@quicinc.com
|
2022-09-13 09:47:35 -05:00 |
|
Taniya Das
|
be9439df23
|
dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280
Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks
for SC7280. Update reg property min/max items in YAML schema.
Fixes: 4185b27b3b ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com
|
2022-09-13 09:47:35 -05:00 |
|
Neal Liu
|
dffc3c566b
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dt-bindings: clock: Add AST2500/AST2600 HACE reset definition
Add HACE reset bit definition for AST2500/AST2600.
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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2022-08-26 18:50:38 +08:00 |
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