Commit Graph

453 Commits

Author SHA1 Message Date
Eric Chanudet
b8ae88e1e7 mailbox: qcom-ipcc: flag IRQ NO_THREAD
PREEMPT_RT forces qcom-ipcc's handler to be threaded with interrupts
enabled, which triggers a warning in __handle_irq_event_percpu():
    irq 173 handler irq_default_primary_handler+0x0/0x10 enabled interrupts
    WARNING: CPU: 0 PID: 77 at kernel/irq/handle.c:161 __handle_irq_event_percpu+0x4c4/0x4d0

Mark it IRQF_NO_THREAD to avoid running the handler in a threaded
context with threadirqs or PREEMPT_RT enabled.

Signed-off-by: Eric Chanudet <echanude@redhat.com>
Acked-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:51:58 -05:00
Colin Ian King
8ac1111055 mailbox: pcc: Fix spelling mistake "Plaform" -> "Platform"
There is a spelling mistake in a pr_err message. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:51:14 -05:00
Jack Wang
6b207ce8a9 mailbox: bcm-ferxrm-mailbox: Fix error check for dma_map_sg
dma_map_sg return 0 on error, fix the error check, and return -EIO
to caller.

Fixes: dbc049eee7 ("mailbox: Add driver for Broadcom FlexRM ring manager")
Signed-off-by: Jack Wang <jinpu.wang@ionos.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:50:53 -05:00
Robert Marko
f5fe925df8 mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock support
IPQ8074 has the APSS clock controller utilizing the same register space as
the APCS, so provide access to the APSS utilizing a child device like
IPQ6018.

IPQ6018 and IPQ8074 use the same controller and driver, so just utilize
IPQ6018 match data for IPQ8074.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:50:01 -05:00
Conor Dooley
0d1aadfe10 mailbox: mpfs: account for mbox offsets while sending
The mailbox offset is not only used for receiving messages, but it is
also used by messages sent to the system controller by Linux that have a
payload, such as the "digital signature service". It is also overloaded
by certain other services (reprogramming of the FPGA fabric, see Link:)
to have a meaning other than the offset the system controller should
read from.
When the driver was written, no such services of the latter type were
in use & those of the former used an offset of zero so this has gone
un-noticed.

Link: https://www.microsemi.com/document-portal/doc_download/1245815-polarfire-fpga-and-polarfire-soc-fpga-system-services-user-guide # Section 5.2
Fixes: 83d7b15608 ("mbox: add polarfire soc system controller mailbox")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:48:38 -05:00
Conor Dooley
2e10289d1f mailbox: mpfs: fix handling of the reg property
The "data" region of the PolarFire SoC's system controller mailbox is
not one continuous register space - the system controller's QSPI sits
between the control and data registers. Split the "data" reg into two
parts: "data" & "control". Optionally get the "data" register address
from the 3rd reg property in the devicetree & fall back to using the
old base + MAILBOX_REG_OFFSET that the current code uses.

Fixes: 83d7b15608 ("mbox: add polarfire soc system controller mailbox")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:48:31 -05:00
Peng Fan
7e5cd064f7 mailbox: imx: fix RST channel support
Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated
to include the CR register. Add the missed CR register to xcr array.

Fixes: 82ab513bae ("mailbox: imx: support RST channel")
Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com> # i.MX8qm/qxp MEK boards boot
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-10-05 21:46:36 -05:00
Hector Martin
68584e380e mailbox: apple: Implement poll_data() operation
This allows clients running in atomic context to poll for messages to
arrive.

Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-09-15 13:14:01 -05:00
Hector Martin
38ed8c888e mailbox: apple: Implement flush() operation
This allows clients to use the atomic-safe mailbox API style.

Signed-off-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-09-15 13:14:01 -05:00
Linus Torvalds
92ceebf920 Merge tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar:

 - mtk:
     - use rx_callback instead of cmdq_task_cb

 - qcom:
     - add syscon const
     - add SM6375 compatible

 - imx:
     - enable RST channel
     - clear pending irqs

* tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: imx: clear pending interrupts
  dt-bindings: mailbox: qcom-ipcc: Add SM6375 compatible
  mailbox: imx: support RST channel
  dt-bindings: mailbox: imx-mu: add RST channel
  dt-bindings: mailbox: qcom,apcs-kpss-global: Add syscon const for relevant entries
  mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb
2022-08-08 10:19:40 -07:00
Peng Fan
8a8dc2b959 mailbox: imx: clear pending interrupts
During MU initialization, there maybe pending GSR and RSR pending
interrupt, clear them to avoid unexpected kernel dump when requesting
mailbox channel

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-08-03 09:48:13 -05:00
Peng Fan
82ab513bae mailbox: imx: support RST channel
i.MX generic MU supports MU-A/B reset feature.

When stop/start remotecore, MU is not reset. So when Linux stop
remotecore, the MU-B side BCR may contain valid configuration,
because MU-B is not reset. So when linux start Mcore
again and notify Mcore, Mcore is not ready to handle MU interrupt
and cause issues. So need reset MU when stop Mcore.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-08-02 15:10:26 -05:00
Chun-Kuang Hu
d9c26e0a58 mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb
rx_callback is a standard mailbox callback mechanism and could cover the
function of proprietary cmdq_task_cb, so use the standard one instead of
the proprietary one. Client driver has changed to use standard
rx_callback, so remove proprietary cmdq_task_cb.

Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-08-02 15:06:57 -05:00
Thomas Gleixner
2aec85b26f treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_30.RULE (part 2)
Based on the normalized pattern:

    this program is free software you can redistribute it and/or modify it
    under the terms of the gnu general public license as published by the
    free software foundation version 2  this program is distributed as is
    without any warranty of any kind whether express or implied without
    even the implied warranty of merchantability or fitness for a
    particular purpose see the gnu general public license for more details

extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

has been chosen to replace the boilerplate/reference.

Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-06-10 14:51:35 +02:00
Nathan Chancellor
79f9fbe303 mailbox: qcom-ipcc: Fix -Wunused-function with CONFIG_PM_SLEEP=n
When CONFIG_PM_SLEEP is not set, there is a warning that
qcom_ipcc_pm_resume() is unused:

  drivers/mailbox/qcom-ipcc.c:258:12: error: 'qcom_ipcc_pm_resume' defined but not used [-Werror=unused-function]
    258 | static int qcom_ipcc_pm_resume(struct device *dev)
        |            ^~~~~~~~~~~~~~~~~~~
  cc1: all warnings being treated as errors

Commit 1a3c7bb088 ("PM: core: Add new *_PM_OPS macros, deprecate old
ones") reworked the PM_OPS macros to avoid this problem. Use
NOIRQ_SYSTEM_SLEEP_PM_OPS directly so that qcom_ipcc_pm_resume() always
appears to be used to the compiler, even though it will be dead code
eliminated in the !CONFIG_PM_SLEEP case.

Fixes: c25f778997 ("mailbox: qcom-ipcc: Log the pending interrupt during resume")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-24 08:08:24 -05:00
Björn Ardö
bca1a10046 mailbox: forward the hrtimer if not queued and under a lock
This reverts commit c7dacf5b0f,
"mailbox: avoid timer start from callback"

The previous commit was reverted since it lead to a race that
caused the hrtimer to not be started at all. The check for
hrtimer_active() in msg_submit() will return true if the
callback function txdone_hrtimer() is currently running. This
function could return HRTIMER_NORESTART and then the timer
will not be restarted, and also msg_submit() will not start
the timer. This will lead to a message actually being submitted
but no timer will start to check for its compleation.

The original fix that added checking hrtimer_active() was added to
avoid a warning with hrtimer_forward. Looking in the kernel
another solution to avoid this warning is to check hrtimer_is_queued()
before calling hrtimer_forward_now() instead. This however requires a
lock so the timer is not started by msg_submit() inbetween this check
and the hrtimer_forward() call.

Fixes: c7dacf5b0f ("mailbox: avoid timer start from callback")
Signed-off-by: Björn Ardö <bjorn.ardo@axis.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-23 14:45:24 -05:00
Prasad Sodagudi
c25f778997 mailbox: qcom-ipcc: Log the pending interrupt during resume
Enable logging of the pending interrupt that triggered device wakeup. This
logging information helps to debug IRQs that cause periodic device wakeups
by printing the detailed information of pending IPCC interrupts.

Scenario: Device wakeup caused by Modem crash
Logs:
qcom-ipcc mailbox: virq: 182 triggered client-id: 2; signal-id: 2

From the IPCC bindings it can further be understood that the client here is
IPCC_CLIENT_MPSS and the signal was IPCC_MPROC_SIGNAL_SMP2P.

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Prasad Sodagudi <quic_psodagud@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
Mario Limonciello
369e4ef87a mailbox: pcc: Fix an invalid-load caught by the address sanitizer
`pcc_mailbox_probe` doesn't initialize all memory that has been allocated
before the first time that one of it's members `txdone_irq` may be
accessed.

This leads to a an invalid load any time that this member is accessed:
[    2.429769] UBSAN: invalid-load in drivers/mailbox/pcc.c:684:22
[    2.430324] UBSAN: invalid-load in drivers/mailbox/mailbox.c:486:12
[    4.276782] UBSAN: invalid-load in drivers/acpi/cppc_acpi.c:314:45

Link: https://bugzilla.kernel.org/show_bug.cgi?id=215587
Fixes: ce028702dd ("mailbox: pcc: Move bulk of PCCT parsing into pcc_mbox_probe")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
Krzysztof Kozlowski
a022c7c96c mailbox: correct kerneldoc
Correct kerneldoc warnings like:

  drivers/mailbox/arm_mhu_db.c:47:
    warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
  drivers/mailbox/qcom-ipcc.c:58:
    warning: Function parameter or member 'num_chans' not described in 'qcom_ipcc'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
ran jianping
d951269608 mailbox: omap: using pm_runtime_resume_and_get to simplify the code
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and
pm_runtime_put_noidle. This change is just to simplify the code, no
actual functional changes.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ran jianping <ran.jianping@zte.com.cn>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
ran jianping
504ff5b008 mailbox:imx: using pm_runtime_resume_and_get
Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and
pm_runtime_put_noidle. This change is just to simplify the code, no
actual functional changes.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: ran jianping <ran.jianping@zte.com.cn>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
Tinghan Shen
02b5c35a61 mailbox: mediatek: support mt8186 adsp mailbox
Add support of mt8186 adsp mailbox.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
Kartik
74c20dd0f8 mailbox: tegra-hsp: Add 128-bit shared mailbox support
Add support for 128-bit shared mailboxes found on Tegra234 chips.

Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
Kartik
8f585d1403 mailbox: tegra-hsp: Add tegra_hsp_sm_ops
This patch introduces tegra_hsp_sm_ops to abstract send & receive
API's for shared mailboxes.

Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:30 -05:00
Xiaomeng Tong
1b0070aca3 mailbox: remove an unneeded NULL check on list iterator
The list iterator is always non-NULL so it doesn't need to be checked.
Thus just remove the unnecessary NULL check.

Signed-off-by: Xiaomeng Tong <xiam0nd.tong@gmail.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-05-21 11:41:29 -05:00