mirror of
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synced 2026-03-09 10:07:04 -07:00
drm/amd/display: DML changes for DCN32/321
DML is required for display configuration modelling for things like bandwidth management and validation. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Aurabindo Pillai
committed by
Alex Deucher
Alex Deucher
parent
58efeea32d
commit
dda4fb85e4
@@ -72,6 +72,9 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_ccflags) $(frame_warn_flag)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/dcn30_fpu.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_ccflags) $(frame_warn_flag)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn31/dcn31_fpu.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
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CFLAGS_$(AMDDALPATH)/dc/dml/dcn302/dcn302_fpu.o := $(dml_ccflags)
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@@ -93,6 +96,9 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_mode_vba_31.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn31/display_rq_dlg_calc_31.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_32.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_rq_dlg_calc_32.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn32/display_mode_vba_util_32.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags)
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@@ -116,6 +122,7 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
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DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
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DML += dcn30/dcn30_fpu.o dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
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DML += dcn31/display_mode_vba_31.o dcn31/display_rq_dlg_calc_31.o
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DML += dcn32/display_mode_vba_32.o dcn32/display_rq_dlg_calc_32.o dcn32/display_mode_vba_util_32.o
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DML += dcn31/dcn31_fpu.o
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DML += dcn301/dcn301_fpu.o
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DML += dcn302/dcn302_fpu.o
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@@ -438,8 +438,8 @@ static void UseMinimumDCFCLK(
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int dpte_group_bytes[],
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double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
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double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
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int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
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int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
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int BytePerPixelY[],
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int BytePerPixelC[],
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int HTotal[],
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@@ -6696,8 +6696,8 @@ static void UseMinimumDCFCLK(
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int dpte_group_bytes[],
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double PrefetchLinesY[][2][DC__NUM_DPP__MAX],
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double PrefetchLinesC[][2][DC__NUM_DPP__MAX],
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int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
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int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_luma_ub_all_states[][2][DC__NUM_DPP__MAX],
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unsigned int swath_width_chroma_ub_all_states[][2][DC__NUM_DPP__MAX],
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int BytePerPixelY[],
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int BytePerPixelC[],
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int HTotal[],
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@@ -2996,7 +2996,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
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v->ImmediateFlipSupported)) ? true : false;
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#ifdef __DML_VBA_DEBUG__
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dml_print("DML::%s: PrefetchModeSupported %d\n", __func__, v->PrefetchModeSupported);
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dml_print("DML::%s: ImmediateFlipRequirement %d\n", __func__, v->ImmediateFlipRequirement == dm_immediate_flip_required);
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dml_print("DML::%s: ImmediateFlipRequirement[0] %d\n", __func__, v->ImmediateFlipRequirement[0] == dm_immediate_flip_required);
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dml_print("DML::%s: ImmediateFlipSupported %d\n", __func__, v->ImmediateFlipSupported);
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dml_print("DML::%s: ImmediateFlipSupport %d\n", __func__, v->ImmediateFlipSupport);
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dml_print("DML::%s: HostVMEnable %d\n", __func__, v->HostVMEnable);
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,57 @@
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DML32_DISPLAY_MODE_VBA_H__
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#define __DML32_DISPLAY_MODE_VBA_H__
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#include "../display_mode_enums.h"
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// To enable a lot of debug msg
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//#define __DML_VBA_DEBUG__
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// For DML-C changes that hasn't been propagated to VBA yet
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//#define __DML_VBA_ALLOW_DELTA__
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// Move these to ip parameters/constant
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// At which vstartup the DML start to try if the mode can be supported
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#define __DML_VBA_MIN_VSTARTUP__ 9
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// Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
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#define __DML_ARB_TO_RET_DELAY__ 7 + 95
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// fudge factor for min dcfclk calclation
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#define __DML_MIN_DCFCLK_FACTOR__ 1.15
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// Prefetch schedule max vratio
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#define __DML_MAX_VRATIO_PRE__ 4.0
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#define BPP_INVALID 0
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#define BPP_BLENDED_PIPE 0xffffffff
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struct display_mode_lib;
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void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
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void dml32_recalculate(struct display_mode_lib *mode_lib);
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#endif
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,70 @@
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/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DML32_DISPLAY_RQ_DLG_CALC_H__
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#define __DML32_DISPLAY_RQ_DLG_CALC_H__
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#include "../display_rq_dlg_helpers.h"
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struct display_mode_lib;
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/*
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* Function: dml_rq_dlg_get_rq_reg
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* Main entry point for test to get the register values out of this DML class.
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* This function calls <get_rq_param> and <extract_rq_regs> functions to calculate
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* and then populate the rq_regs struct
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* Input:
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* pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
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* Output:
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* rq_regs - struct that holds all the RQ registers field value.
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* See also: <display_rq_regs_st>
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*/
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void dml32_rq_dlg_get_rq_reg(display_rq_regs_st *rq_regs,
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struct display_mode_lib *mode_lib,
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const display_e2e_pipe_params_st *e2e_pipe_param,
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const unsigned int num_pipes,
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const unsigned int pipe_idx);
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/*
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* Function: dml_rq_dlg_get_dlg_reg
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* Calculate and return DLG and TTU register struct given the system setting
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* Output:
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* dlg_regs - output DLG register struct
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* ttu_regs - output DLG TTU register struct
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* Input:
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* e2e_pipe_param - "compacted" array of e2e pipe param struct
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* num_pipes - num of active "pipe" or "route"
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* pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
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* cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
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* Added for legacy or unrealistic timing tests.
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*/
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void dml32_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
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display_dlg_regs_st *dlg_regs,
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display_ttu_regs_st *ttu_regs,
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display_e2e_pipe_params_st *e2e_pipe_param,
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const unsigned int num_pipes,
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const unsigned int pipe_idx);
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#endif
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@@ -26,7 +26,11 @@
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#define __DISPLAY_MODE_ENUMS_H__
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enum output_encoder_class {
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dm_dp = 0, dm_hdmi = 1, dm_wb = 2, dm_edp
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dm_dp = 0,
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dm_hdmi = 1,
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dm_wb = 2,
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dm_edp = 3,
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dm_dp2p0 = 5,
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};
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enum output_format_class {
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dm_444 = 0, dm_420 = 1, dm_n422, dm_s422
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@@ -105,6 +109,10 @@ enum clock_change_support {
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dm_dram_clock_change_uninitialized = 0,
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dm_dram_clock_change_vactive,
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dm_dram_clock_change_vblank,
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dm_dram_clock_change_vactive_w_mall_full_frame,
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dm_dram_clock_change_vactive_w_mall_sub_vp,
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dm_dram_clock_change_vblank_w_mall_full_frame,
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dm_dram_clock_change_vblank_w_mall_sub_vp,
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dm_dram_clock_change_unsupported
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};
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@@ -169,6 +177,9 @@ enum odm_combine_mode {
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dm_odm_combine_mode_disabled,
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dm_odm_combine_mode_2to1,
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dm_odm_combine_mode_4to1,
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dm_odm_split_mode_1to2,
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dm_odm_mode_mso_1to2,
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dm_odm_mode_mso_1to4
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};
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enum odm_combine_policy {
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@@ -176,11 +187,15 @@ enum odm_combine_policy {
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dm_odm_combine_policy_none,
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dm_odm_combine_policy_2to1,
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dm_odm_combine_policy_4to1,
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dm_odm_split_policy_1to2,
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dm_odm_mso_policy_1to2,
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dm_odm_mso_policy_1to4,
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};
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enum immediate_flip_requirement {
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dm_immediate_flip_not_required,
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dm_immediate_flip_required,
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dm_immediate_flip_opportunistic,
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};
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enum unbounded_requesting_policy {
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@@ -189,4 +204,75 @@ enum unbounded_requesting_policy {
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dm_unbounded_requesting_disable
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};
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enum dm_rotation_angle {
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dm_rotation_0,
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dm_rotation_90,
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dm_rotation_180,
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dm_rotation_270,
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dm_rotation_0m,
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dm_rotation_90m,
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dm_rotation_180m,
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dm_rotation_270m,
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};
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enum dm_use_mall_for_pstate_change_mode {
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dm_use_mall_pstate_change_disable,
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dm_use_mall_pstate_change_full_frame,
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dm_use_mall_pstate_change_sub_viewport,
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dm_use_mall_pstate_change_phantom_pipe
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};
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enum dm_use_mall_for_static_screen_mode {
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dm_use_mall_static_screen_disable,
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dm_use_mall_static_screen_optimize,
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dm_use_mall_static_screen_enable,
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};
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enum dm_output_link_dp_rate {
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dm_dp_rate_na,
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dm_dp_rate_hbr,
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dm_dp_rate_hbr2,
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dm_dp_rate_hbr3,
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dm_dp_rate_uhbr10,
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dm_dp_rate_uhbr13p5,
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dm_dp_rate_uhbr20,
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};
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enum dm_fclock_change_support {
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dm_fclock_change_vactive,
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dm_fclock_change_vblank,
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dm_fclock_change_unsupported,
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};
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enum dm_prefetch_modes {
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dm_prefetch_support_uclk_fclk_and_stutter_if_possible,
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dm_prefetch_support_uclk_fclk_and_stutter,
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dm_prefetch_support_fclk_and_stutter,
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dm_prefetch_support_stutter,
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dm_prefetch_support_none,
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};
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enum dm_output_type {
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dm_output_type_unknown,
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dm_output_type_dp,
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dm_output_type_edp,
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dm_output_type_dp2p0,
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dm_output_type_hdmi,
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dm_output_type_hdmifrl,
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};
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enum dm_output_rate {
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dm_output_rate_unknown,
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dm_output_rate_dp_rate_hbr,
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dm_output_rate_dp_rate_hbr2,
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dm_output_rate_dp_rate_hbr3,
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dm_output_rate_dp_rate_uhbr10,
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dm_output_rate_dp_rate_uhbr13p5,
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dm_output_rate_dp_rate_uhbr20,
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dm_output_rate_hdmi_rate_3x3,
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dm_output_rate_hdmi_rate_6x3,
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dm_output_rate_hdmi_rate_6x4,
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dm_output_rate_hdmi_rate_8x4,
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dm_output_rate_hdmi_rate_10x4,
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dm_output_rate_hdmi_rate_12x4,
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};
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#endif
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@@ -35,6 +35,8 @@
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#include "dcn30/display_rq_dlg_calc_30.h"
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#include "dcn31/display_mode_vba_31.h"
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#include "dcn31/display_rq_dlg_calc_31.h"
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#include "dcn32/display_mode_vba_32.h"
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#include "dcn32/display_rq_dlg_calc_32.h"
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#include "dml_logger.h"
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const struct dml_funcs dml20_funcs = {
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@@ -72,6 +74,13 @@ const struct dml_funcs dml31_funcs = {
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.rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg
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};
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const struct dml_funcs dml32_funcs = {
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.validate = dml32_ModeSupportAndSystemConfigurationFull,
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.recalculate = dml32_recalculate,
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.rq_dlg_get_dlg_reg_v2 = dml32_rq_dlg_get_dlg_reg,
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.rq_dlg_get_rq_reg_v2 = dml32_rq_dlg_get_rq_reg
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};
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void dml_init_instance(struct display_mode_lib *lib,
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const struct _vcs_dpi_soc_bounding_box_st *soc_bb,
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const struct _vcs_dpi_ip_params_st *ip_params,
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@@ -98,6 +107,9 @@ void dml_init_instance(struct display_mode_lib *lib,
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case DML_PROJECT_DCN31_FPGA:
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lib->funcs = dml31_funcs;
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break;
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case DML_PROJECT_DCN32:
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lib->funcs = dml32_funcs;
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break;
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default:
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break;
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@@ -41,6 +41,7 @@ enum dml_project {
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DML_PROJECT_DCN30,
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DML_PROJECT_DCN31,
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DML_PROJECT_DCN31_FPGA,
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DML_PROJECT_DCN32,
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};
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struct display_mode_lib;
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||||
@@ -62,6 +63,20 @@ struct dml_funcs {
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_rq_regs_st *rq_regs,
|
||||
const display_pipe_params_st *pipe_param);
|
||||
// DLG interfaces have different function parameters in DCN32.
|
||||
// Create new function pointers to address the changes
|
||||
void (*rq_dlg_get_dlg_reg_v2)(
|
||||
struct display_mode_lib *mode_lib,
|
||||
display_dlg_regs_st *dlg_regs,
|
||||
display_ttu_regs_st *ttu_regs,
|
||||
display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx);
|
||||
void (*rq_dlg_get_rq_reg_v2)(display_rq_regs_st *rq_regs,
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *e2e_pipe_param,
|
||||
const unsigned int num_pipes,
|
||||
const unsigned int pipe_idx);
|
||||
void (*recalculate)(struct display_mode_lib *mode_lib);
|
||||
void (*validate)(struct display_mode_lib *mode_lib);
|
||||
};
|
||||
|
||||
@@ -54,12 +54,102 @@ typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st;
|
||||
typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st;
|
||||
typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st;
|
||||
|
||||
typedef struct {
|
||||
double UrgentWatermark;
|
||||
double WritebackUrgentWatermark;
|
||||
double DRAMClockChangeWatermark;
|
||||
double FCLKChangeWatermark;
|
||||
double WritebackDRAMClockChangeWatermark;
|
||||
double WritebackFCLKChangeWatermark;
|
||||
double StutterExitWatermark;
|
||||
double StutterEnterPlusExitWatermark;
|
||||
double Z8StutterExitWatermark;
|
||||
double Z8StutterEnterPlusExitWatermark;
|
||||
double USRRetrainingWatermark;
|
||||
} Watermarks;
|
||||
|
||||
typedef struct {
|
||||
double UrgentLatency;
|
||||
double ExtraLatency;
|
||||
double WritebackLatency;
|
||||
double DRAMClockChangeLatency;
|
||||
double FCLKChangeLatency;
|
||||
double SRExitTime;
|
||||
double SREnterPlusExitTime;
|
||||
double SRExitZ8Time;
|
||||
double SREnterPlusExitZ8Time;
|
||||
double USRRetrainingLatencyPlusSMNLatency;
|
||||
} Latencies;
|
||||
|
||||
typedef struct {
|
||||
double Dppclk;
|
||||
double Dispclk;
|
||||
double PixelClock;
|
||||
double DCFClkDeepSleep;
|
||||
unsigned int DPPPerSurface;
|
||||
bool ScalerEnabled;
|
||||
enum dm_rotation_angle SourceRotation;
|
||||
unsigned int ViewportHeight;
|
||||
unsigned int ViewportHeightChroma;
|
||||
unsigned int BlockWidth256BytesY;
|
||||
unsigned int BlockHeight256BytesY;
|
||||
unsigned int BlockWidth256BytesC;
|
||||
unsigned int BlockHeight256BytesC;
|
||||
unsigned int BlockWidthY;
|
||||
unsigned int BlockHeightY;
|
||||
unsigned int BlockWidthC;
|
||||
unsigned int BlockHeightC;
|
||||
unsigned int InterlaceEnable;
|
||||
unsigned int NumberOfCursors;
|
||||
unsigned int VBlank;
|
||||
unsigned int HTotal;
|
||||
unsigned int HActive;
|
||||
bool DCCEnable;
|
||||
enum odm_combine_mode ODMMode;
|
||||
enum source_format_class SourcePixelFormat;
|
||||
enum dm_swizzle_mode SurfaceTiling;
|
||||
unsigned int BytePerPixelY;
|
||||
unsigned int BytePerPixelC;
|
||||
bool ProgressiveToInterlaceUnitInOPP;
|
||||
double VRatio;
|
||||
double VRatioChroma;
|
||||
unsigned int VTaps;
|
||||
unsigned int VTapsChroma;
|
||||
unsigned int PitchY;
|
||||
unsigned int DCCMetaPitchY;
|
||||
unsigned int PitchC;
|
||||
unsigned int DCCMetaPitchC;
|
||||
bool ViewportStationary;
|
||||
unsigned int ViewportXStart;
|
||||
unsigned int ViewportYStart;
|
||||
unsigned int ViewportXStartC;
|
||||
unsigned int ViewportYStartC;
|
||||
bool FORCE_ONE_ROW_FOR_FRAME;
|
||||
unsigned int SwathHeightY;
|
||||
unsigned int SwathHeightC;
|
||||
} DmlPipe;
|
||||
|
||||
typedef struct {
|
||||
double UrgentLatency;
|
||||
double ExtraLatency;
|
||||
double WritebackLatency;
|
||||
double DRAMClockChangeLatency;
|
||||
double FCLKChangeLatency;
|
||||
double SRExitTime;
|
||||
double SREnterPlusExitTime;
|
||||
double SRExitZ8Time;
|
||||
double SREnterPlusExitZ8Time;
|
||||
double USRRetrainingLatency;
|
||||
double SMNLatency;
|
||||
} SOCParametersList;
|
||||
|
||||
struct _vcs_dpi_voltage_scaling_st {
|
||||
int state;
|
||||
double dscclk_mhz;
|
||||
double dcfclk_mhz;
|
||||
double socclk_mhz;
|
||||
double phyclk_d18_mhz;
|
||||
double phyclk_d32_mhz;
|
||||
double dram_speed_mts;
|
||||
double fabricclk_mhz;
|
||||
double dispclk_mhz;
|
||||
@@ -80,6 +170,15 @@ struct _vcs_dpi_soc_bounding_box_st {
|
||||
double urgent_latency_pixel_data_only_us;
|
||||
double urgent_latency_pixel_mixed_with_vm_data_us;
|
||||
double urgent_latency_vm_data_only_us;
|
||||
double usr_retraining_latency_us;
|
||||
double smn_latency_us;
|
||||
double fclk_change_latency_us;
|
||||
double mall_allocated_for_dcn_mbytes;
|
||||
double pct_ideal_fabric_bw_after_urgent;
|
||||
double pct_ideal_dram_bw_after_urgent_strobe;
|
||||
double max_avg_fabric_bw_use_normal_percent;
|
||||
double max_avg_dram_bw_use_normal_strobe_percent;
|
||||
enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final;
|
||||
double writeback_latency_us;
|
||||
double ideal_dram_bw_after_urgent_percent;
|
||||
double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
|
||||
@@ -148,6 +247,9 @@ struct _vcs_dpi_ip_params_st {
|
||||
unsigned int dpp_output_buffer_pixels;
|
||||
unsigned int opp_output_buffer_lines;
|
||||
unsigned int pixel_chunk_size_kbytes;
|
||||
unsigned int alpha_pixel_chunk_size_kbytes;
|
||||
unsigned int min_pixel_chunk_size_bytes;
|
||||
unsigned int dcc_meta_buffer_size_bytes;
|
||||
unsigned char pte_enable;
|
||||
unsigned int pte_chunk_size_kbytes;
|
||||
unsigned int meta_chunk_size_kbytes;
|
||||
@@ -168,6 +270,7 @@ struct _vcs_dpi_ip_params_st {
|
||||
double writeback_min_hscl_ratio;
|
||||
double writeback_min_vscl_ratio;
|
||||
unsigned int maximum_dsc_bits_per_component;
|
||||
unsigned int maximum_pixels_per_line_per_dsc_unit;
|
||||
unsigned int writeback_max_hscl_taps;
|
||||
unsigned int writeback_max_vscl_taps;
|
||||
unsigned int writeback_line_buffer_luma_buffer_size;
|
||||
@@ -224,6 +327,8 @@ struct _vcs_dpi_ip_params_st {
|
||||
unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one;
|
||||
unsigned int bug_forcing_LC_req_same_size_fixed;
|
||||
unsigned int number_of_cursors;
|
||||
unsigned int max_num_dp2p0_outputs;
|
||||
unsigned int max_num_dp2p0_streams;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_xfc_params_st {
|
||||
@@ -250,6 +355,7 @@ struct _vcs_dpi_display_pipe_source_params_st {
|
||||
bool hostvm_levels_force_en;
|
||||
unsigned int hostvm_levels_force;
|
||||
int source_scan;
|
||||
int source_rotation; // new in dml32
|
||||
int sw_mode;
|
||||
int macro_tile_size;
|
||||
unsigned int surface_width_y;
|
||||
@@ -264,6 +370,15 @@ struct _vcs_dpi_display_pipe_source_params_st {
|
||||
unsigned int viewport_height_c;
|
||||
unsigned int viewport_width_max;
|
||||
unsigned int viewport_height_max;
|
||||
unsigned int viewport_x_y;
|
||||
unsigned int viewport_x_c;
|
||||
bool viewport_stationary;
|
||||
unsigned int dcc_rate_luma;
|
||||
unsigned int gpuvm_min_page_size_kbytes;
|
||||
unsigned int use_mall_for_pstate_change;
|
||||
unsigned int use_mall_for_static_screen;
|
||||
bool force_one_row_for_frame;
|
||||
bool pte_buffer_mode;
|
||||
unsigned int data_pitch;
|
||||
unsigned int data_pitch_c;
|
||||
unsigned int meta_pitch;
|
||||
@@ -296,10 +411,17 @@ struct writeback_st {
|
||||
int wb_vtaps_luma;
|
||||
int wb_htaps_chroma;
|
||||
int wb_vtaps_chroma;
|
||||
unsigned int wb_htaps;
|
||||
unsigned int wb_vtaps;
|
||||
double wb_hratio;
|
||||
double wb_vratio;
|
||||
};
|
||||
|
||||
struct display_audio_params_st {
|
||||
unsigned int audio_sample_rate_khz;
|
||||
int audio_sample_layout;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_output_params_st {
|
||||
int dp_lanes;
|
||||
double output_bpp;
|
||||
@@ -313,6 +435,11 @@ struct _vcs_dpi_display_output_params_st {
|
||||
int dsc_slices;
|
||||
int max_audio_sample_rate;
|
||||
struct writeback_st wb;
|
||||
struct display_audio_params_st audio;
|
||||
unsigned int output_bpc;
|
||||
int dp_rate;
|
||||
unsigned int dp_multistream_id;
|
||||
bool dp_multistream_en;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_scaler_ratio_depth_st {
|
||||
@@ -361,6 +488,8 @@ struct _vcs_dpi_display_pipe_dest_params_st {
|
||||
unsigned char use_maximum_vstartup;
|
||||
unsigned int vtotal_max;
|
||||
unsigned int vtotal_min;
|
||||
unsigned int refresh_rate;
|
||||
bool synchronize_timings;
|
||||
};
|
||||
|
||||
struct _vcs_dpi_display_pipe_params_st {
|
||||
@@ -558,6 +687,9 @@ struct _vcs_dpi_display_arb_params_st {
|
||||
int max_req_outstanding;
|
||||
int min_req_outstanding;
|
||||
int sat_level_us;
|
||||
int hvm_min_req_outstand_commit_threshold;
|
||||
int hvm_max_qos_commit_threshold;
|
||||
int compbuf_reserved_space_kbytes;
|
||||
};
|
||||
|
||||
#endif /*__DISPLAY_MODE_STRUCTS_H__*/
|
||||
|
||||
@@ -110,6 +110,15 @@ dml_get_attr_func(return_bw, mode_lib->vba.ReturnBW);
|
||||
dml_get_attr_func(tcalc, mode_lib->vba.TCalc);
|
||||
dml_get_attr_func(fraction_of_urgent_bandwidth, mode_lib->vba.FractionOfUrgentBandwidth);
|
||||
dml_get_attr_func(fraction_of_urgent_bandwidth_imm_flip, mode_lib->vba.FractionOfUrgentBandwidthImmediateFlip);
|
||||
dml_get_attr_func(cstate_max_cap_mode, mode_lib->vba.DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE);
|
||||
dml_get_attr_func(comp_buffer_size_kbytes, mode_lib->vba.CompressedBufferSizeInkByte);
|
||||
dml_get_attr_func(pixel_chunk_size_in_kbyte, mode_lib->vba.PixelChunkSizeInKByte);
|
||||
dml_get_attr_func(alpha_pixel_chunk_size_in_kbyte, mode_lib->vba.AlphaPixelChunkSizeInKByte);
|
||||
dml_get_attr_func(meta_chunk_size_in_kbyte, mode_lib->vba.MetaChunkSize);
|
||||
dml_get_attr_func(min_pixel_chunk_size_in_byte, mode_lib->vba.MinPixelChunkSizeBytes);
|
||||
dml_get_attr_func(min_meta_chunk_size_in_byte, mode_lib->vba.MinMetaChunkSizeBytes);
|
||||
dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
|
||||
dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRetrainingWatermark);
|
||||
|
||||
#define dml_get_pipe_attr_func(attr, var) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
|
||||
{\
|
||||
@@ -165,6 +174,27 @@ dml_get_pipe_attr_func(vupdate_width, mode_lib->vba.VUpdateWidthPix);
|
||||
dml_get_pipe_attr_func(vready_offset, mode_lib->vba.VReadyOffsetPix);
|
||||
dml_get_pipe_attr_func(vready_at_or_after_vsync, mode_lib->vba.VREADY_AT_OR_AFTER_VSYNC);
|
||||
dml_get_pipe_attr_func(min_dst_y_next_start, mode_lib->vba.MIN_DST_Y_NEXT_START);
|
||||
dml_get_pipe_attr_func(dst_y_per_pte_row_nom_l, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_L);
|
||||
dml_get_pipe_attr_func(dst_y_per_pte_row_nom_c, mode_lib->vba.DST_Y_PER_PTE_ROW_NOM_C);
|
||||
dml_get_pipe_attr_func(dst_y_per_meta_row_nom_l, mode_lib->vba.DST_Y_PER_META_ROW_NOM_L);
|
||||
dml_get_pipe_attr_func(dst_y_per_meta_row_nom_c, mode_lib->vba.DST_Y_PER_META_ROW_NOM_C);
|
||||
dml_get_pipe_attr_func(refcyc_per_pte_group_nom_l_in_us, mode_lib->vba.time_per_pte_group_nom_luma);
|
||||
dml_get_pipe_attr_func(refcyc_per_pte_group_nom_c_in_us, mode_lib->vba.time_per_pte_group_nom_chroma);
|
||||
dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_l_in_us, mode_lib->vba.time_per_pte_group_vblank_luma);
|
||||
dml_get_pipe_attr_func(refcyc_per_pte_group_vblank_c_in_us, mode_lib->vba.time_per_pte_group_vblank_chroma);
|
||||
dml_get_pipe_attr_func(refcyc_per_pte_group_flip_l_in_us, mode_lib->vba.time_per_pte_group_flip_luma);
|
||||
dml_get_pipe_attr_func(refcyc_per_pte_group_flip_c_in_us, mode_lib->vba.time_per_pte_group_flip_chroma);
|
||||
dml_get_pipe_attr_func(vstartup_calculated, mode_lib->vba.VStartup);
|
||||
dml_get_pipe_attr_func(dpte_row_height_linear_c, mode_lib->vba.dpte_row_height_linear_chroma);
|
||||
dml_get_pipe_attr_func(swath_height_l, mode_lib->vba.SwathHeightY);
|
||||
dml_get_pipe_attr_func(swath_height_c, mode_lib->vba.SwathHeightC);
|
||||
dml_get_pipe_attr_func(det_stored_buffer_size_l_bytes, mode_lib->vba.DETBufferSizeY);
|
||||
dml_get_pipe_attr_func(det_stored_buffer_size_c_bytes, mode_lib->vba.DETBufferSizeC);
|
||||
dml_get_pipe_attr_func(dpte_group_size_in_bytes, mode_lib->vba.dpte_group_bytes);
|
||||
dml_get_pipe_attr_func(vm_group_size_in_bytes, mode_lib->vba.vm_group_bytes);
|
||||
dml_get_pipe_attr_func(dpte_row_height_linear_l, mode_lib->vba.dpte_row_height_linear);
|
||||
dml_get_pipe_attr_func(pte_buffer_mode, mode_lib->vba.PTE_BUFFER_MODE);
|
||||
dml_get_pipe_attr_func(subviewport_lines_needed_in_mall, mode_lib->vba.SubViewportLinesNeededInMALL);
|
||||
|
||||
double get_total_immediate_flip_bytes(
|
||||
struct display_mode_lib *mode_lib,
|
||||
@@ -202,6 +232,67 @@ double get_total_prefetch_bw(
|
||||
return total_prefetch_bw;
|
||||
}
|
||||
|
||||
unsigned int get_total_surface_size_in_mall_bytes(
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes)
|
||||
{
|
||||
unsigned int k;
|
||||
unsigned int size = 0.0;
|
||||
recalculate_params(mode_lib, pipes, num_pipes);
|
||||
for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k)
|
||||
size += mode_lib->vba.SurfaceSizeInMALL[k];
|
||||
return size;
|
||||
}
|
||||
|
||||
unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx)
|
||||
{
|
||||
int pipe_idx = -1;
|
||||
int i;
|
||||
|
||||
ASSERT(plane_idx < DC__NUM_DPP__MAX);
|
||||
|
||||
for (i = 0; i < DC__NUM_DPP__MAX ; i++) {
|
||||
if (plane_idx == mode_lib->vba.pipe_plane[i]) {
|
||||
pipe_idx = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
ASSERT(pipe_idx >= 0);
|
||||
|
||||
return pipe_idx;
|
||||
}
|
||||
|
||||
|
||||
double get_det_buffer_size_kbytes(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes, unsigned int pipe_idx)
|
||||
{
|
||||
unsigned int plane_idx;
|
||||
double det_buf_size_kbytes;
|
||||
|
||||
recalculate_params(mode_lib, pipes, num_pipes);
|
||||
plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
|
||||
|
||||
dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plane_idx);
|
||||
det_buf_size_kbytes = mode_lib->vba.DETBufferSizeInKByte[plane_idx]; // per hubp DET buffer size
|
||||
|
||||
dml_print("DML::%s: det_buf_size_kbytes=%3.2f\n", __func__, det_buf_size_kbytes);
|
||||
|
||||
return det_buf_size_kbytes;
|
||||
}
|
||||
|
||||
bool get_is_phantom_pipe(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes, unsigned int pipe_idx)
|
||||
{
|
||||
unsigned int plane_idx;
|
||||
|
||||
recalculate_params(mode_lib, pipes, num_pipes);
|
||||
plane_idx = mode_lib->vba.pipe_plane[pipe_idx];
|
||||
dml_print("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx,
|
||||
mode_lib->vba.UsesMALLForPStateChange[plane_idx]);
|
||||
return (mode_lib->vba.UsesMALLForPStateChange[plane_idx] == dm_use_mall_pstate_change_phantom_pipe);
|
||||
}
|
||||
|
||||
static void fetch_socbb_params(struct display_mode_lib *mode_lib)
|
||||
{
|
||||
soc_bounding_box_st *soc = &mode_lib->vba.soc;
|
||||
@@ -241,6 +332,22 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
|
||||
soc->max_avg_sdp_bw_use_normal_percent;
|
||||
mode_lib->vba.SRExitZ8Time = soc->sr_exit_z8_time_us;
|
||||
mode_lib->vba.SREnterPlusExitZ8Time = soc->sr_enter_plus_exit_z8_time_us;
|
||||
mode_lib->vba.FCLKChangeLatency = soc->fclk_change_latency_us;
|
||||
mode_lib->vba.USRRetrainingLatency = soc->usr_retraining_latency_us;
|
||||
mode_lib->vba.SMNLatency = soc->smn_latency_us;
|
||||
mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes;
|
||||
|
||||
mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe;
|
||||
mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation =
|
||||
soc->max_avg_fabric_bw_use_normal_percent;
|
||||
mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE =
|
||||
soc->max_avg_dram_bw_use_normal_strobe_percent;
|
||||
|
||||
mode_lib->vba.DRAMClockChangeRequirementFinal = 1;
|
||||
mode_lib->vba.FCLKChangeRequirementFinal = 1;
|
||||
mode_lib->vba.USRRetrainingRequiredFinal = 1;
|
||||
mode_lib->vba.ConfigurableDETSizeEnFinal = 0;
|
||||
mode_lib->vba.AllowForPStateChangeOrStutterInVBlankFinal = soc->allow_for_pstate_or_stutter_in_vblank_final;
|
||||
mode_lib->vba.DRAMClockChangeLatency = soc->dram_clock_change_latency_us;
|
||||
mode_lib->vba.DummyPStateCheck = soc->dram_clock_change_latency_us == soc->dummy_pstate_latency_us;
|
||||
mode_lib->vba.DRAMClockChangeSupportsVActive = !soc->disable_dram_clock_change_vactive_support ||
|
||||
@@ -283,6 +390,7 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
|
||||
mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz;
|
||||
mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz;
|
||||
mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz;
|
||||
mode_lib->vba.PHYCLKD32PerState[i] = soc->clock_limits[i].phyclk_d32_mhz;
|
||||
mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz;
|
||||
mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz;
|
||||
mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts;
|
||||
@@ -325,6 +433,18 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
|
||||
mode_lib->vba.COMPBUF_RESERVED_SPACE_ZS = ip->compbuf_reserved_space_zs;
|
||||
mode_lib->vba.MaximumDSCBitsPerComponent = ip->maximum_dsc_bits_per_component;
|
||||
mode_lib->vba.DSC422NativeSupport = ip->dsc422_native_support;
|
||||
/* In DCN3.2, nomDETInKByte should be initialized correctly. */
|
||||
mode_lib->vba.nomDETInKByte = ip->det_buffer_size_kbytes;
|
||||
mode_lib->vba.CompbufReservedSpace64B = ip->compbuf_reserved_space_64b;
|
||||
mode_lib->vba.CompbufReservedSpaceZs = ip->compbuf_reserved_space_zs;
|
||||
mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal = ip->compressed_buffer_segment_size_in_kbytes;
|
||||
mode_lib->vba.LineBufferSizeFinal = ip->line_buffer_size_bits;
|
||||
mode_lib->vba.AlphaPixelChunkSizeInKByte = ip->alpha_pixel_chunk_size_kbytes; // not ysed
|
||||
mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes; // not used
|
||||
mode_lib->vba.MaximumPixelsPerLinePerDSCUnit = ip->maximum_pixels_per_line_per_dsc_unit;
|
||||
mode_lib->vba.MaxNumDP2p0Outputs = ip->max_num_dp2p0_outputs;
|
||||
mode_lib->vba.MaxNumDP2p0Streams = ip->max_num_dp2p0_streams;
|
||||
mode_lib->vba.DCCMetaBufferSizeBytes = ip->dcc_meta_buffer_size_bytes;
|
||||
|
||||
mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
|
||||
mode_lib->vba.MetaChunkSize = ip->meta_chunk_size_kbytes;
|
||||
@@ -399,6 +519,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
|
||||
visited[k] = false;
|
||||
|
||||
mode_lib->vba.NumberOfActivePlanes = 0;
|
||||
mode_lib->vba.NumberOfActiveSurfaces = 0;
|
||||
mode_lib->vba.ImmediateFlipSupport = false;
|
||||
for (j = 0; j < mode_lib->vba.cache_num_pipes; ++j) {
|
||||
display_pipe_source_params_st *src = &pipes[j].pipe.src;
|
||||
@@ -429,6 +550,21 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
|
||||
src->viewport_y_y;
|
||||
mode_lib->vba.ViewportYStartC[mode_lib->vba.NumberOfActivePlanes] =
|
||||
src->viewport_y_c;
|
||||
mode_lib->vba.SourceRotation[mode_lib->vba.NumberOfActiveSurfaces] = src->source_rotation;
|
||||
mode_lib->vba.ViewportXStartY[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_y;
|
||||
mode_lib->vba.ViewportXStartC[mode_lib->vba.NumberOfActiveSurfaces] = src->viewport_x_c;
|
||||
// TODO: Assign correct value to viewport_stationary
|
||||
mode_lib->vba.ViewportStationary[mode_lib->vba.NumberOfActivePlanes] =
|
||||
src->viewport_stationary;
|
||||
mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_pstate_change;
|
||||
mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_static_screen;
|
||||
mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes] = src->gpuvm_min_page_size_kbytes;
|
||||
mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] = dst->refresh_rate; //todo remove this
|
||||
mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = dout->dp_rate;
|
||||
mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] = dst->odm_combine;
|
||||
//TODO: Need to assign correct values to dp_multistream vars
|
||||
mode_lib->vba.OutputMultistreamEn[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_en;
|
||||
mode_lib->vba.OutputMultistreamId[mode_lib->vba.NumberOfActiveSurfaces] = dout->dp_multistream_id;
|
||||
mode_lib->vba.PitchY[mode_lib->vba.NumberOfActivePlanes] = src->data_pitch;
|
||||
mode_lib->vba.SurfaceWidthY[mode_lib->vba.NumberOfActivePlanes] = src->surface_width_y;
|
||||
mode_lib->vba.SurfaceHeightY[mode_lib->vba.NumberOfActivePlanes] = src->surface_height_y;
|
||||
@@ -677,6 +813,7 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
|
||||
}
|
||||
|
||||
mode_lib->vba.NumberOfActivePlanes++;
|
||||
mode_lib->vba.NumberOfActiveSurfaces++;
|
||||
}
|
||||
|
||||
// handle overlays through BlendingAndTiming
|
||||
@@ -702,6 +839,8 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
|
||||
}
|
||||
}
|
||||
|
||||
mode_lib->vba.SynchronizeTimingsFinal = pipes[0].pipe.dest.synchronize_timings;
|
||||
mode_lib->vba.DCCProgrammingAssumesScanDirectionUnknownFinal = false;
|
||||
mode_lib->vba.UseUnboundedRequesting = dm_unbounded_requesting;
|
||||
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
|
||||
if (pipes[k].pipe.src.unbounded_req_mode == 0)
|
||||
@@ -745,6 +884,32 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
|
||||
|
||||
mode_lib->vba.GPUVMEnable = mode_lib->vba.GPUVMEnable && !!ip->gpuvm_enable;
|
||||
mode_lib->vba.HostVMEnable = mode_lib->vba.HostVMEnable && !!ip->hostvm_enable;
|
||||
|
||||
for (k = 0; k < mode_lib->vba.cache_num_pipes; ++k) {
|
||||
mode_lib->vba.ForceOneRowForFrame[k] = pipes[k].pipe.src.force_one_row_for_frame;
|
||||
mode_lib->vba.PteBufferMode[k] = pipes[k].pipe.src.pte_buffer_mode;
|
||||
|
||||
if (mode_lib->vba.PteBufferMode[k] == 0 && mode_lib->vba.GPUVMEnable) {
|
||||
if (mode_lib->vba.ForceOneRowForFrame[k] ||
|
||||
(mode_lib->vba.GPUVMMinPageSizeKBytes[k] > 64*1024) ||
|
||||
(mode_lib->vba.UsesMALLForPStateChange[k] != dm_use_mall_pstate_change_disable) ||
|
||||
(mode_lib->vba.UseMALLForStaticScreen[k] != dm_use_mall_static_screen_disable)) {
|
||||
#ifdef __DML_VBA_DEBUG__
|
||||
dml_print("DML::%s: ERROR: Invalid PteBufferMode=%d for plane %0d!\n",
|
||||
__func__, mode_lib->vba.PteBufferMode[k], k);
|
||||
dml_print("DML::%s: - ForceOneRowForFrame = %d\n",
|
||||
__func__, mode_lib->vba.ForceOneRowForFrame[k]);
|
||||
dml_print("DML::%s: - GPUVMMinPageSizeKBytes = %d\n",
|
||||
__func__, mode_lib->vba.GPUVMMinPageSizeKBytes[k]);
|
||||
dml_print("DML::%s: - UseMALLForPStateChange = %d\n",
|
||||
__func__, (int) mode_lib->vba.UsesMALLForPStateChange[k]);
|
||||
dml_print("DML::%s: - UseMALLForStaticScreen = %d\n",
|
||||
__func__, (int) mode_lib->vba.UseMALLForStaticScreen[k]);
|
||||
#endif
|
||||
ASSERT(0);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -896,6 +1061,7 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
|
||||
soc_bounding_box_st *soc = &mode_lib->vba.soc;
|
||||
unsigned int k;
|
||||
unsigned int total_pipes = 0;
|
||||
unsigned int pipe_idx = 0;
|
||||
|
||||
mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage;
|
||||
mode_lib->vba.ReturnBW = mode_lib->vba.ReturnBWPerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb];
|
||||
@@ -917,6 +1083,11 @@ void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib)
|
||||
// Total Available Pipes Support Check
|
||||
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
|
||||
total_pipes += mode_lib->vba.DPPPerPlane[k];
|
||||
pipe_idx = get_pipe_idx(mode_lib, k);
|
||||
if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0)
|
||||
mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz;
|
||||
else
|
||||
mode_lib->vba.DPPCLK[k] = soc->clock_limits[mode_lib->vba.VoltageLevel].dppclk_mhz;
|
||||
}
|
||||
ASSERT(total_pipes <= DC__NUM_DPP__MAX);
|
||||
}
|
||||
|
||||
@@ -58,6 +58,15 @@ dml_get_attr_decl(return_bw);
|
||||
dml_get_attr_decl(tcalc);
|
||||
dml_get_attr_decl(fraction_of_urgent_bandwidth);
|
||||
dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
|
||||
dml_get_attr_decl(cstate_max_cap_mode);
|
||||
dml_get_attr_decl(comp_buffer_size_kbytes);
|
||||
dml_get_attr_decl(pixel_chunk_size_in_kbyte);
|
||||
dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
|
||||
dml_get_attr_decl(meta_chunk_size_in_kbyte);
|
||||
dml_get_attr_decl(min_pixel_chunk_size_in_byte);
|
||||
dml_get_attr_decl(min_meta_chunk_size_in_byte);
|
||||
dml_get_attr_decl(fclk_watermark);
|
||||
dml_get_attr_decl(usr_retraining_watermark);
|
||||
|
||||
#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
|
||||
|
||||
@@ -75,6 +84,26 @@ dml_get_pipe_attr_decl(dst_y_per_row_vblank);
|
||||
dml_get_pipe_attr_decl(dst_y_prefetch);
|
||||
dml_get_pipe_attr_decl(dst_y_per_vm_flip);
|
||||
dml_get_pipe_attr_decl(dst_y_per_row_flip);
|
||||
dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
|
||||
dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
|
||||
dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
|
||||
dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
|
||||
dml_get_pipe_attr_decl(dpte_row_height_linear_c);
|
||||
dml_get_pipe_attr_decl(swath_height_l);
|
||||
dml_get_pipe_attr_decl(swath_height_c);
|
||||
dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
|
||||
dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
|
||||
dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
|
||||
dml_get_pipe_attr_decl(vm_group_size_in_bytes);
|
||||
dml_get_pipe_attr_decl(det_buffer_size_kbytes);
|
||||
dml_get_pipe_attr_decl(dpte_row_height_linear_l);
|
||||
dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
|
||||
dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
|
||||
dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
|
||||
dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
|
||||
dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
|
||||
dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
|
||||
dml_get_pipe_attr_decl(pte_buffer_mode);
|
||||
dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
|
||||
dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
|
||||
dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
|
||||
@@ -108,6 +137,8 @@ dml_get_pipe_attr_decl(vupdate_width);
|
||||
dml_get_pipe_attr_decl(vready_offset);
|
||||
dml_get_pipe_attr_decl(vready_at_or_after_vsync);
|
||||
dml_get_pipe_attr_decl(min_dst_y_next_start);
|
||||
dml_get_pipe_attr_decl(vstartup_calculated);
|
||||
dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
|
||||
|
||||
double get_total_immediate_flip_bytes(
|
||||
struct display_mode_lib *mode_lib,
|
||||
@@ -126,6 +157,16 @@ unsigned int dml_get_voltage_level(
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
|
||||
unsigned int get_total_surface_size_in_mall_bytes(
|
||||
struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes);
|
||||
unsigned int get_pipe_idx(struct display_mode_lib *mode_lib, unsigned int plane_idx);
|
||||
|
||||
bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
|
||||
const display_e2e_pipe_params_st *pipes,
|
||||
unsigned int num_pipes,
|
||||
unsigned int pipe_idx);
|
||||
void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
|
||||
|
||||
bool Calculate256BBlockSizes(
|
||||
@@ -138,6 +179,39 @@ bool Calculate256BBlockSizes(
|
||||
unsigned int *BlockWidth256BytesY,
|
||||
unsigned int *BlockWidth256BytesC);
|
||||
|
||||
struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
|
||||
unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
|
||||
double dummy_single_array[2][DC__NUM_DPP__MAX];
|
||||
unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
|
||||
double dummy_double_array[2][DC__NUM_DPP__MAX];
|
||||
bool dummy_boolean_array[DC__NUM_DPP__MAX];
|
||||
bool dummy_boolean;
|
||||
bool dummy_boolean2;
|
||||
enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
|
||||
DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
|
||||
bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
|
||||
unsigned int ReorderBytes;
|
||||
unsigned int VMDataOnlyReturnBW;
|
||||
double HostVMInefficiencyFactor;
|
||||
};
|
||||
|
||||
struct dml32_ModeSupportAndSystemConfigurationFull {
|
||||
unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX];
|
||||
double dummy_double_array[2][DC__NUM_DPP__MAX];
|
||||
DmlPipe SurfParameters[DC__NUM_DPP__MAX];
|
||||
double dummy_single[5];
|
||||
double dummy_single2[5];
|
||||
SOCParametersList mSOCParameters;
|
||||
unsigned int MaximumSwathWidthSupportLuma;
|
||||
unsigned int MaximumSwathWidthSupportChroma;
|
||||
};
|
||||
|
||||
struct dummy_vars {
|
||||
struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
|
||||
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
|
||||
struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
|
||||
};
|
||||
|
||||
struct vba_vars_st {
|
||||
ip_params_st ip;
|
||||
soc_bounding_box_st soc;
|
||||
@@ -154,6 +228,7 @@ struct vba_vars_st {
|
||||
double DISPCLKWithRampingRoundedToDFSGranularity;
|
||||
double DISPCLKWithoutRampingRoundedToDFSGranularity;
|
||||
double MaxDispclkRoundedToDFSGranularity;
|
||||
double MaxDppclkRoundedToDFSGranularity;
|
||||
bool DCCEnabledAnyPlane;
|
||||
double ReturnBandwidthToDCN;
|
||||
unsigned int TotalActiveDPP;
|
||||
@@ -169,6 +244,8 @@ struct vba_vars_st {
|
||||
double NextMaxVStartup;
|
||||
double VBlankTime;
|
||||
double SmallestVBlank;
|
||||
enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
|
||||
double DCFCLKDeepSleepPerSurface[DC__NUM_DPP__MAX];
|
||||
double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
|
||||
double EffectiveDETPlusLBLinesLuma;
|
||||
double EffectiveDETPlusLBLinesChroma;
|
||||
@@ -212,6 +289,14 @@ struct vba_vars_st {
|
||||
double UrgentLatencyPixelMixedWithVMData;
|
||||
double UrgentLatencyVMDataOnly;
|
||||
double UrgentLatency; // max of the above three
|
||||
double USRRetrainingLatency;
|
||||
double SMNLatency;
|
||||
double FCLKChangeLatency;
|
||||
unsigned int MALLAllocatedForDCNFinal;
|
||||
double DefaultGPUVMMinPageSizeKBytes; // Default for the project
|
||||
double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
|
||||
double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
|
||||
double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
|
||||
double WritebackLatency;
|
||||
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
|
||||
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
|
||||
@@ -284,6 +369,14 @@ struct vba_vars_st {
|
||||
double DPPCLKDelayCNVCCursor;
|
||||
double DISPCLKDelaySubtotal;
|
||||
bool ProgressiveToInterlaceUnitInOPP;
|
||||
unsigned int CompressedBufferSegmentSizeInkByteFinal;
|
||||
unsigned int CompbufReservedSpace64B;
|
||||
unsigned int CompbufReservedSpaceZs;
|
||||
unsigned int LineBufferSizeFinal;
|
||||
unsigned int MaximumPixelsPerLinePerDSCUnit;
|
||||
unsigned int AlphaPixelChunkSizeInKByte;
|
||||
double MinPixelChunkSizeBytes;
|
||||
unsigned int DCCMetaBufferSizeBytes;
|
||||
// Pipe/Plane Parameters
|
||||
int VoltageLevel;
|
||||
double FabricClock;
|
||||
@@ -291,6 +384,23 @@ struct vba_vars_st {
|
||||
double DISPCLK;
|
||||
double SOCCLK;
|
||||
double DCFCLK;
|
||||
unsigned int MaxTotalDETInKByte;
|
||||
unsigned int MinCompressedBufferSizeInKByte;
|
||||
unsigned int NumberOfActiveSurfaces;
|
||||
bool ViewportStationary[DC__NUM_DPP__MAX];
|
||||
unsigned int RefreshRate[DC__NUM_DPP__MAX];
|
||||
double OutputBPP[DC__NUM_DPP__MAX];
|
||||
unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
|
||||
bool SynchronizeTimingsFinal;
|
||||
bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
|
||||
bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
|
||||
unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
|
||||
unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
|
||||
enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
|
||||
bool DRRDisplay[DC__NUM_DPP__MAX];
|
||||
bool PteBufferMode[DC__NUM_DPP__MAX];
|
||||
enum dm_output_type OutputType[DC__NUM_DPP__MAX];
|
||||
enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
|
||||
|
||||
unsigned int NumberOfActivePlanes;
|
||||
unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
|
||||
@@ -392,6 +502,12 @@ struct vba_vars_st {
|
||||
double StutterEfficiencyNotIncludingVBlank;
|
||||
double NonUrgentLatencyTolerance;
|
||||
double MinActiveDRAMClockChangeLatencySupported;
|
||||
double Z8StutterEfficiencyBestCase;
|
||||
unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
|
||||
double Z8StutterEfficiencyNotIncludingVBlankBestCase;
|
||||
double StutterPeriodBestCase;
|
||||
Watermarks Watermark;
|
||||
bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
|
||||
|
||||
// These are the clocks calcuated by the library but they are not actually
|
||||
// used explicitly. They are fetched by tests and then possibly used. The
|
||||
@@ -399,6 +515,10 @@ struct vba_vars_st {
|
||||
double DISPCLK_calculated;
|
||||
double DPPCLK_calculated[DC__NUM_DPP__MAX];
|
||||
|
||||
bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
|
||||
|
||||
bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
|
||||
bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
|
||||
unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
|
||||
double VUpdateWidthPix[DC__NUM_DPP__MAX];
|
||||
double VReadyOffsetPix[DC__NUM_DPP__MAX];
|
||||
@@ -429,6 +549,7 @@ struct vba_vars_st {
|
||||
double DRAMSpeedPerState[DC__VOLTAGE_STATES];
|
||||
double MaxDispclk[DC__VOLTAGE_STATES];
|
||||
int VoltageOverrideLevel;
|
||||
double PHYCLKD32PerState[DC__VOLTAGE_STATES];
|
||||
|
||||
/*outputs*/
|
||||
bool ScaleRatioAndTapsSupport;
|
||||
@@ -452,6 +573,51 @@ struct vba_vars_st {
|
||||
bool PitchSupport;
|
||||
enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
|
||||
|
||||
/* Mode Support Reason */
|
||||
bool P2IWith420;
|
||||
bool DSCOnlyIfNecessaryWithBPP;
|
||||
bool DSC422NativeNotSupported;
|
||||
bool LinkRateDoesNotMatchDPVersion;
|
||||
bool LinkRateForMultistreamNotIndicated;
|
||||
bool BPPForMultistreamNotIndicated;
|
||||
bool MultistreamWithHDMIOreDP;
|
||||
bool MSOOrODMSplitWithNonDPLink;
|
||||
bool NotEnoughLanesForMSO;
|
||||
bool ViewportExceedsSurface;
|
||||
|
||||
bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
|
||||
bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
|
||||
bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
|
||||
bool InvalidCombinationOfMALLUseForPState;
|
||||
|
||||
enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
|
||||
double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
|
||||
double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
|
||||
double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
|
||||
double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
|
||||
double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
|
||||
double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
|
||||
double MetaRowBytesThisState[DC__NUM_DPP__MAX];
|
||||
bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
|
||||
bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
|
||||
|
||||
unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
|
||||
double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileHeightY[DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileHeightC[DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileWidthY[DC__NUM_DPP__MAX];
|
||||
unsigned int MicroTileWidthC[DC__NUM_DPP__MAX];
|
||||
bool ImmediateFlipRequiredFinal;
|
||||
bool DCCProgrammingAssumesScanDirectionUnknownFinal;
|
||||
bool EnoughWritebackUnits;
|
||||
bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
|
||||
bool NumberOfDP2p0Support;
|
||||
unsigned int MaxNumDP2p0Streams;
|
||||
unsigned int MaxNumDP2p0Outputs;
|
||||
enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
|
||||
enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
|
||||
double WritebackLineBufferLumaBufferSize;
|
||||
double WritebackLineBufferChromaBufferSize;
|
||||
double WritebackMinHSCLRatio;
|
||||
@@ -647,6 +813,7 @@ struct vba_vars_st {
|
||||
double dummy7[DC__NUM_DPP__MAX];
|
||||
double dummy8[DC__NUM_DPP__MAX];
|
||||
double dummy13[DC__NUM_DPP__MAX];
|
||||
double dummy_double_array[2][DC__NUM_DPP__MAX];
|
||||
unsigned int dummyinteger1ms[DC__NUM_DPP__MAX];
|
||||
double dummyinteger2ms[DC__NUM_DPP__MAX];
|
||||
unsigned int dummyinteger3[DC__NUM_DPP__MAX];
|
||||
@@ -666,6 +833,9 @@ struct vba_vars_st {
|
||||
unsigned int dummyintegerarr2[DC__NUM_DPP__MAX];
|
||||
unsigned int dummyintegerarr3[DC__NUM_DPP__MAX];
|
||||
unsigned int dummyintegerarr4[DC__NUM_DPP__MAX];
|
||||
unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX];
|
||||
unsigned int dummy_integer_array22[22][DC__NUM_DPP__MAX];
|
||||
|
||||
bool dummysinglestring;
|
||||
bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
|
||||
double PlaneRequiredDISPCLKWithODMCombine2To1;
|
||||
@@ -896,8 +1066,8 @@ struct vba_vars_st {
|
||||
double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
|
||||
unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
@@ -972,6 +1142,74 @@ struct vba_vars_st {
|
||||
int Z8NumberOfStutterBurstsPerFrame;
|
||||
unsigned int MaximumDSCBitsPerComponent;
|
||||
unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
|
||||
double UrgentLatencyWithUSRRetraining;
|
||||
double UrgLatencyWithUSRRetraining[DC__VOLTAGE_STATES];
|
||||
double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
|
||||
double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
|
||||
double SurfaceRequiredDISPCLKWithoutODMCombine;
|
||||
double SurfaceRequiredDISPCLK;
|
||||
double SurfaceRequiredDISPCLKWithODMCombine2To1;
|
||||
double SurfaceRequiredDISPCLKWithODMCombine4To1;
|
||||
double MinActiveFCLKChangeLatencySupported;
|
||||
double dummy14;
|
||||
double dummy15;
|
||||
int MinVoltageLevel;
|
||||
int MaxVoltageLevel;
|
||||
unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
|
||||
unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
|
||||
unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
|
||||
unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
|
||||
unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
|
||||
bool ExceededMALLSize;
|
||||
bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
|
||||
unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
|
||||
unsigned int dummyinteger33;
|
||||
unsigned int CompressedBufferSizeInkByteThisState;
|
||||
enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
|
||||
Latencies myLatency;
|
||||
Latencies mLatency;
|
||||
Watermarks DummyWatermark;
|
||||
bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
|
||||
bool dummyBooleanvector1[DC__NUM_DPP__MAX];
|
||||
bool dummyBooleanvector2[DC__NUM_DPP__MAX];
|
||||
enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
|
||||
bool NotEnoughUrgentLatencyHiding_dml32[DC__VOLTAGE_STATES][2];
|
||||
bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
|
||||
bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
|
||||
enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
|
||||
bool UnboundedRequestEnabledThisState;
|
||||
bool DRAMClockChangeRequirementFinal;
|
||||
bool FCLKChangeRequirementFinal;
|
||||
bool USRRetrainingRequiredFinal;
|
||||
bool MALLUseFinal;
|
||||
bool ConfigurableDETSizeEnFinal;
|
||||
bool dummyboolean;
|
||||
unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
|
||||
unsigned int nomDETInKByte;
|
||||
enum mpc_combine_affinity MPCCombineUse[DC__NUM_DPP__MAX];
|
||||
bool MPCCombineMethodIncompatible;
|
||||
unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
|
||||
bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
|
||||
enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
|
||||
unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
|
||||
bool OutputMultistreamEn[DC__NUM_DPP__MAX];
|
||||
bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
|
||||
double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
|
||||
double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
|
||||
bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
|
||||
bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
|
||||
bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
|
||||
bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
|
||||
bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
|
||||
unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
|
||||
unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
|
||||
unsigned int BlockHeightY[DC__NUM_DPP__MAX];
|
||||
unsigned int BlockHeightC[DC__NUM_DPP__MAX];
|
||||
unsigned int BlockWidthY[DC__NUM_DPP__MAX];
|
||||
unsigned int BlockWidthC[DC__NUM_DPP__MAX];
|
||||
unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
|
||||
bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
|
||||
struct dummy_vars dummy_vars;
|
||||
};
|
||||
|
||||
bool CalculateMinAndMaxPrefetchMode(
|
||||
|
||||
@@ -23,7 +23,6 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include "dml_wrapper.h"
|
||||
#include "resource.h"
|
||||
#include "core_types.h"
|
||||
#include "dsc.h"
|
||||
@@ -86,25 +85,6 @@ static void get_pixel_clock_parameters(
|
||||
|
||||
}
|
||||
|
||||
static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
|
||||
{
|
||||
get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
|
||||
|
||||
if (pipe_ctx->clock_source)
|
||||
pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
|
||||
pipe_ctx->clock_source,
|
||||
&pipe_ctx->stream_res.pix_clk_params,
|
||||
&pipe_ctx->pll_settings);
|
||||
|
||||
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
|
||||
|
||||
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
|
||||
&pipe_ctx->stream->bit_depth_params);
|
||||
build_clamping_params(pipe_ctx->stream);
|
||||
|
||||
return DC_OK;
|
||||
}
|
||||
|
||||
static void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
|
||||
struct bit_depth_reduction_params *fmt_bit_depth)
|
||||
{
|
||||
@@ -231,6 +211,30 @@ static void resource_build_bit_depth_reduction_params(struct dc_stream_state *st
|
||||
fmt_bit_depth->pixel_encoding = pixel_encoding;
|
||||
}
|
||||
|
||||
/* Move this after the above function as VS complains about
|
||||
* declaration issues for resource_build_bit_depth_reduction_params.
|
||||
*/
|
||||
|
||||
static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
|
||||
{
|
||||
|
||||
get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
|
||||
|
||||
if (pipe_ctx->clock_source)
|
||||
pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
|
||||
pipe_ctx->clock_source,
|
||||
&pipe_ctx->stream_res.pix_clk_params,
|
||||
&pipe_ctx->pll_settings);
|
||||
|
||||
pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
|
||||
|
||||
resource_build_bit_depth_reduction_params(pipe_ctx->stream,
|
||||
&pipe_ctx->stream->bit_depth_params);
|
||||
build_clamping_params(pipe_ctx->stream);
|
||||
|
||||
return DC_OK;
|
||||
}
|
||||
|
||||
bool dml_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
|
||||
{
|
||||
int i;
|
||||
@@ -1130,7 +1134,7 @@ static int dml_populate_dml_pipes_from_context(
|
||||
{
|
||||
int i, pipe_cnt;
|
||||
struct resource_context *res_ctx = &context->res_ctx;
|
||||
struct pipe_ctx *pipe;
|
||||
struct pipe_ctx *pipe = NULL; // Fix potentially uninitialized error from VS
|
||||
|
||||
populate_dml_pipes_from_context_base(dc, context, pipes, fast_validate);
|
||||
|
||||
@@ -1296,6 +1300,7 @@ static void dml_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
|
||||
context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
|
||||
context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
|
||||
context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
|
||||
context->bw_ctx.dml.soc.fclk_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1593,11 +1598,8 @@ static void dml_calculate_dlg_params(
|
||||
context->bw_ctx.bw.dcn.clk.z9_support = DCN_Z9_SUPPORT_ALLOW;
|
||||
*/
|
||||
context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
|
||||
/* TODO : Uncomment the below line and make changes
|
||||
* as per DML nomenclature once it is available.
|
||||
* context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = context->bw_ctx.dml.vba.fclk_pstate_support;
|
||||
*/
|
||||
|
||||
context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support =
|
||||
context->bw_ctx.dml.vba.FCLKChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
|
||||
if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
|
||||
context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
|
||||
|
||||
@@ -1699,12 +1701,11 @@ static void dml_calculate_wm_and_dlg(
|
||||
context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
//context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
|
||||
/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
|
||||
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 4;
|
||||
context->bw_ctx.bw.dcn.watermarks.b.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
|
||||
//context->bw_ctx.bw.dcn.watermarks.b.usr_retraining = context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns / 8;
|
||||
|
||||
/* Set D:
|
||||
* All clocks min.
|
||||
@@ -1736,13 +1737,11 @@ static void dml_calculate_wm_and_dlg(
|
||||
context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
//context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
|
||||
/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
|
||||
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 4;
|
||||
context->bw_ctx.bw.dcn.watermarks.d.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
|
||||
|
||||
//context->bw_ctx.bw.dcn.watermarks.d.usr_retraining = context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns / 8;
|
||||
/* Set C, for Dummy P-State:
|
||||
* All clocks min.
|
||||
* DCFCLK: Min, as reported by PM FW, when available
|
||||
@@ -1773,13 +1772,11 @@ static void dml_calculate_wm_and_dlg(
|
||||
context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
//context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_wm_fclk_pstate(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = get_fclk_watermark(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = get_wm_usr_retraining(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||
|
||||
/* Temporary, to have some fclk_pstate_change_ns and usr_retraining_ns wm values until DML is implemented */
|
||||
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.fclk_pstate_change_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 4;
|
||||
context->bw_ctx.bw.dcn.watermarks.c.usr_retraining_ns = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
|
||||
|
||||
//context->bw_ctx.bw.dcn.watermarks.c.usr_retraining = context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns / 8;
|
||||
if ((!pstate_en) && (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid)) {
|
||||
/* The only difference between A and C is p-state latency, if p-state is not supported
|
||||
* with full p-state latency we want to calculate DLG based on dummy p-state latency,
|
||||
|
||||
Reference in New Issue
Block a user