mirror of
https://github.com/ukui/kernel.git
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Merge tag 'sound-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
Pull sound updates from Takashi Iwai:
"As the diffstat scatters over the tree, we've got many tree-wide small
changes, but also got quite a few intrusive changes in the core side.
The only ABI-visible core change is the new rawmidi framing mode
support while others are kernel-internal, mostly code refactoring
and/or nice improvements.
Here are some highlights:
Core:
- A new framing access mode for rawmidi to get timestamps
- Cleanup / refactoring of buffer memory management helper code
- Support for automatic negotiation of ASoC DAI formats
- Revival of software suspend for PCM and control core, as a
preliminary work for PCI BAR rescan support
ASoC:
- Accessory detection support for several Qualcomm parts
- Support for IEC958 control with hdmi-codec
- Merging of Tegra machine drivers into a single driver
- Support for AmLogic SM1 TOACODEC, Intel AlderLake-M, several NXP
i.MX8 variants, NXP TFA1 and TDF9897, Rockchip RK817, Qualcomm
Quinary MI2S, Texas Instruments TAS2505
USB-audio:
- Reduction of latency at playback start
- Code cleanup / fixes of usx2y driver
- Scarlett2 mixer code fixes and enhancements
- Quirks for Ozone and Denon devices
HD-audio:
- A few quirks for HP and ASUS machines
- Display power management fixes
Others:
- FireWire code refactoring and enhancements
- Tree-wide trivial coding-style fixes"
* tag 'sound-5.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (594 commits)
ALSA: usb-audio: scarlett2: Fix for loop increment in scarlett2_usb_get_config
ALSA: hda/realtek: fix mute/micmute LEDs for HP ProBook 630 G8
ALSA: hda/realtek: fix mute/micmute LEDs for HP ProBook 445 G8
ALSA: hda/realtek: fix mute/micmute LEDs for HP ProBook 450 G8
ALSA: hda/realtek - Add ALC285 HP init procedure
ALSA: hda/realtek - Add type for ALC287
ALSA: scarlett2: Fix scarlett2_*_ctl_put() return values again
ALSA: scarlett2: Fix pad count for 18i8 Gen 3
ALSA: hda/realtek: fix mute/micmute LEDs for HP EliteBook 830 G8 Notebook PC
ALSA: firewire-lib: Fix 'amdtp_domain_start()' when no AMDTP_OUT_STREAM stream is found
ASoC: qcom: lpass-cpu: mark IRQ_CLEAR register as volatile and readable
ALSA: hda: Release codec display power during shutdown/reboot
ALSA: hda: Release controller display power during shutdown/reboot
ALSA: hda/realtek: Apply LED fixup for HP Dragonfly G1, too
ASoC: fsl: remove unnecessary oom message
ASoC: tlv320aic32x4: dt-bindings: add TAS2505 to compatible
ASoC: tlv320aic32x4: add support for TAS2505
ASoC: tlv320aic32x4: add type to device private data struct
ASoC: tegra30: ahub: Use devm_platform_get_and_ioremap_resource()
ASoC: tegra: tegra210_admaif: Use devm_platform_get_and_ioremap_resource()
...
This commit is contained in:
Linus Torvalds
@@ -437,6 +437,87 @@ enum rk809_reg_id {
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#define RK817_RTC_COMP_LSB_REG 0x10
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#define RK817_RTC_COMP_MSB_REG 0x11
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/* RK817 Codec Registers */
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#define RK817_CODEC_DTOP_VUCTL 0x12
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#define RK817_CODEC_DTOP_VUCTIME 0x13
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#define RK817_CODEC_DTOP_LPT_SRST 0x14
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#define RK817_CODEC_DTOP_DIGEN_CLKE 0x15
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#define RK817_CODEC_AREF_RTCFG0 0x16
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#define RK817_CODEC_AREF_RTCFG1 0x17
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#define RK817_CODEC_AADC_CFG0 0x18
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#define RK817_CODEC_AADC_CFG1 0x19
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#define RK817_CODEC_DADC_VOLL 0x1a
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#define RK817_CODEC_DADC_VOLR 0x1b
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#define RK817_CODEC_DADC_SR_ACL0 0x1e
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#define RK817_CODEC_DADC_ALC1 0x1f
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#define RK817_CODEC_DADC_ALC2 0x20
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#define RK817_CODEC_DADC_NG 0x21
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#define RK817_CODEC_DADC_HPF 0x22
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#define RK817_CODEC_DADC_RVOLL 0x23
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#define RK817_CODEC_DADC_RVOLR 0x24
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#define RK817_CODEC_AMIC_CFG0 0x27
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#define RK817_CODEC_AMIC_CFG1 0x28
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#define RK817_CODEC_DMIC_PGA_GAIN 0x29
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#define RK817_CODEC_DMIC_LMT1 0x2a
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#define RK817_CODEC_DMIC_LMT2 0x2b
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#define RK817_CODEC_DMIC_NG1 0x2c
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#define RK817_CODEC_DMIC_NG2 0x2d
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#define RK817_CODEC_ADAC_CFG0 0x2e
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#define RK817_CODEC_ADAC_CFG1 0x2f
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#define RK817_CODEC_DDAC_POPD_DACST 0x30
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#define RK817_CODEC_DDAC_VOLL 0x31
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#define RK817_CODEC_DDAC_VOLR 0x32
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#define RK817_CODEC_DDAC_SR_LMT0 0x35
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#define RK817_CODEC_DDAC_LMT1 0x36
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#define RK817_CODEC_DDAC_LMT2 0x37
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#define RK817_CODEC_DDAC_MUTE_MIXCTL 0x38
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#define RK817_CODEC_DDAC_RVOLL 0x39
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#define RK817_CODEC_DDAC_RVOLR 0x3a
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#define RK817_CODEC_AHP_ANTI0 0x3b
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#define RK817_CODEC_AHP_ANTI1 0x3c
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#define RK817_CODEC_AHP_CFG0 0x3d
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#define RK817_CODEC_AHP_CFG1 0x3e
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#define RK817_CODEC_AHP_CP 0x3f
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#define RK817_CODEC_ACLASSD_CFG1 0x40
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#define RK817_CODEC_ACLASSD_CFG2 0x41
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#define RK817_CODEC_APLL_CFG0 0x42
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#define RK817_CODEC_APLL_CFG1 0x43
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#define RK817_CODEC_APLL_CFG2 0x44
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#define RK817_CODEC_APLL_CFG3 0x45
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#define RK817_CODEC_APLL_CFG4 0x46
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#define RK817_CODEC_APLL_CFG5 0x47
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#define RK817_CODEC_DI2S_CKM 0x48
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#define RK817_CODEC_DI2S_RSD 0x49
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#define RK817_CODEC_DI2S_RXCR1 0x4a
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#define RK817_CODEC_DI2S_RXCR2 0x4b
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#define RK817_CODEC_DI2S_RXCMD_TSD 0x4c
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#define RK817_CODEC_DI2S_TXCR1 0x4d
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#define RK817_CODEC_DI2S_TXCR2 0x4e
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#define RK817_CODEC_DI2S_TXCR3_TXCMD 0x4f
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/* RK817_CODEC_DI2S_CKM */
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#define RK817_I2S_MODE_MASK (0x1 << 0)
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#define RK817_I2S_MODE_MST (0x1 << 0)
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#define RK817_I2S_MODE_SLV (0x0 << 0)
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/* RK817_CODEC_DDAC_MUTE_MIXCTL */
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#define DACMT_MASK (0x1 << 0)
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#define DACMT_ENABLE (0x1 << 0)
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#define DACMT_DISABLE (0x0 << 0)
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/* RK817_CODEC_DI2S_RXCR2 */
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#define VDW_RX_24BITS (0x17)
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#define VDW_RX_16BITS (0x0f)
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/* RK817_CODEC_DI2S_TXCR2 */
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#define VDW_TX_24BITS (0x17)
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#define VDW_TX_16BITS (0x0f)
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/* RK817_CODEC_AMIC_CFG0 */
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#define MIC_DIFF_MASK (0x1 << 7)
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#define MIC_DIFF_DIS (0x0 << 7)
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#define MIC_DIFF_EN (0x1 << 7)
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#define RK817_POWER_EN_REG(i) (0xb1 + (i))
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#define RK817_POWER_SLP_EN_REG(i) (0xb5 + (i))
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@@ -18,6 +18,8 @@
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#define WCD934X_EFUSE_SENSE_STATE_DEF 0x10
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#define WCD934X_EFUSE_SENSE_EN_MASK BIT(0)
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#define WCD934X_EFUSE_SENSE_ENABLE BIT(0)
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#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 0x002a
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#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 0x002b
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#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14 0x0037
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#define WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15 0x0038
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#define WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS 0x0039
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@@ -103,21 +105,58 @@
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#define WCD934X_ANA_AMIC3 0x0610
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#define WCD934X_ANA_AMIC4 0x0611
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#define WCD934X_ANA_MBHC_MECH 0x0614
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#define WCD934X_MBHC_L_DET_EN_MASK BIT(7)
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#define WCD934X_MBHC_L_DET_EN BIT(7)
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#define WCD934X_MBHC_GND_DET_EN_MASK BIT(6)
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#define WCD934X_MBHC_MECH_DETECT_TYPE_MASK BIT(5)
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#define WCD934X_MBHC_MECH_DETECT_TYPE_INS 1
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#define WCD934X_MBHC_HPHL_PLUG_TYPE_MASK BIT(4)
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#define WCD934X_MBHC_HPHL_PLUG_TYPE_NO 1
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#define WCD934X_MBHC_GND_PLUG_TYPE_MASK BIT(3)
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#define WCD934X_MBHC_GND_PLUG_TYPE_NO 1
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#define WCD934X_MBHC_HSL_PULLUP_COMP_EN BIT(2)
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#define WCD934X_MBHC_HSG_PULLUP_COMP_EN BIT(1)
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#define WCD934X_MBHC_HPHL_100K_TO_GND_EN BIT(0)
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#define WCD934X_ANA_MBHC_ELECT 0x0615
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#define WCD934X_ANA_MBHC_BIAS_EN_MASK BIT(0)
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#define WCD934X_ANA_MBHC_BIAS_EN BIT(0)
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#define WCD934X_ANA_MBHC_ZDET 0x0616
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#define WCD934X_ANA_MBHC_RESULT_1 0x0617
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#define WCD934X_ANA_MBHC_RESULT_2 0x0618
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#define WCD934X_ANA_MBHC_RESULT_3 0x0619
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#define WCD934X_ANA_MBHC_BTN0 0x061a
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#define WCD934X_VTH_MASK GENMASK(7, 2)
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#define WCD934X_ANA_MBHC_BTN1 0x061b
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#define WCD934X_ANA_MBHC_BTN2 0x061c
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#define WCD934X_ANA_MBHC_BTN3 0x061d
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#define WCD934X_ANA_MBHC_BTN4 0x061e
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#define WCD934X_ANA_MBHC_BTN5 0x061f
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#define WCD934X_ANA_MBHC_BTN6 0x0620
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#define WCD934X_ANA_MBHC_BTN7 0x0621
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#define WCD934X_MBHC_BTN_VTH_MASK GENMASK(7, 2)
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#define WCD934X_ANA_MICB1 0x0622
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#define WCD934X_MICB_VAL_MASK GENMASK(5, 0)
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#define WCD934X_ANA_MICB_EN_MASK GENMASK(7, 6)
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#define WCD934X_MICB_DISABLE 0
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#define WCD934X_MICB_ENABLE 1
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#define WCD934X_MICB_PULL_UP 2
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#define WCD934X_MICB_PULL_DOWN 3
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#define WCD934X_ANA_MICB_PULL_UP 0x80
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#define WCD934X_ANA_MICB_ENABLE 0x40
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#define WCD934X_ANA_MICB_DISABLE 0x0
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#define WCD934X_ANA_MICB2 0x0623
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#define WCD934X_ANA_MICB2_ENABLE BIT(6)
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#define WCD934X_ANA_MICB2_ENABLE_MASK GENMASK(7, 6)
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#define WCD934X_ANA_MICB2_VOUT_MASK GENMASK(5, 0)
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#define WCD934X_ANA_MICB2_RAMP 0x0624
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#define WCD934X_RAMP_EN_MASK BIT(7)
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#define WCD934X_RAMP_SHIFT_CTRL_MASK GENMASK(4, 2)
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#define WCD934X_ANA_MICB3 0x0625
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#define WCD934X_ANA_MICB4 0x0626
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#define WCD934X_BIAS_VBG_FINE_ADJ 0x0629
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#define WCD934X_MBHC_CTL_CLK 0x0656
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#define WCD934X_MBHC_CTL_BCS 0x065a
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#define WCD934X_MBHC_STATUS_SPARE_1 0x065b
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#define WCD934X_MICB1_TEST_CTL_1 0x066b
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#define WCD934X_MICB1_TEST_CTL_2 0x066c
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#define WCD934X_MICB2_TEST_CTL_1 0x066e
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@@ -141,7 +180,11 @@
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#define WCD934X_HPH_CNP_WG_CTL 0x06cc
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#define WCD934X_HPH_GM3_BOOST_EN_MASK BIT(7)
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#define WCD934X_HPH_GM3_BOOST_ENABLE BIT(7)
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#define WCD934X_HPH_CNP_WG_TIME 0x06cd
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#define WCD934X_HPH_OCP_CTL 0x06ce
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#define WCD934X_HPH_PA_CTL2 0x06d2
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#define WCD934X_HPHPA_GND_R_MASK BIT(6)
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#define WCD934X_HPHPA_GND_L_MASK BIT(4)
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#define WCD934X_HPH_L_EN 0x06d3
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#define WCD934X_HPH_GAIN_SRC_SEL_MASK BIT(5)
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#define WCD934X_HPH_GAIN_SRC_SEL_COMPANDER 0
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@@ -152,6 +195,8 @@
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#define WCD934X_HPH_OCP_DET_MASK BIT(0)
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#define WCD934X_HPH_OCP_DET_ENABLE BIT(0)
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#define WCD934X_HPH_OCP_DET_DISABLE 0
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#define WCD934X_HPH_R_ATEST 0x06d8
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#define WCD934X_HPHPA_GND_OVR_MASK BIT(1)
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#define WCD934X_DIFF_LO_LO2_COMPANDER 0x06ea
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#define WCD934X_DIFF_LO_LO1_COMPANDER 0x06eb
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#define WCD934X_CLK_SYS_MCLK_PRG 0x0711
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@@ -172,7 +217,19 @@
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#define WCD934X_SIDO_NEW_VOUT_D_FREQ2 0x071e
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#define WCD934X_SIDO_RIPPLE_FREQ_EN_MASK BIT(0)
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#define WCD934X_SIDO_RIPPLE_FREQ_ENABLE BIT(0)
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#define WCD934X_MBHC_NEW_CTL_1 0x0720
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#define WCD934X_MBHC_CTL_RCO_EN_MASK BIT(7)
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#define WCD935X_MBHC_CTL_RCO_EN BIT(7)
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#define WCD934X_MBHC_NEW_CTL_2 0x0721
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#define WCD934X_M_RTH_CTL_MASK GENMASK(3, 2)
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#define WCD934X_MBHC_NEW_PLUG_DETECT_CTL 0x0722
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#define WCD934X_HSDET_PULLUP_C_MASK GENMASK(7, 6)
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#define WCD934X_MBHC_NEW_ZDET_ANA_CTL 0x0723
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#define WCD934X_ZDET_RANGE_CTL_MASK GENMASK(3, 0)
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#define WCD934X_ZDET_MAXV_CTL_MASK GENMASK(6, 4)
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#define WCD934X_MBHC_NEW_ZDET_RAMP_CTL 0x0724
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#define WCD934X_MBHC_NEW_FSM_STATUS 0x0725
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#define WCD934X_MBHC_NEW_ADC_RESULT 0x0726
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#define WCD934X_TX_NEW_AMIC_4_5_SEL 0x0727
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#define WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L 0x0733
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#define WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL 0x0735
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