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net: lan966x: add port module support
This patch adds support for netdev and phylink in the switch. The injection + extraction is register based. This will be replaced with DMA accees. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Horatiu Vultur
committed by
David S. Miller
David S. Miller
parent
db8bcaad53
commit
d28d6d2e37
@@ -5,4 +5,4 @@
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obj-$(CONFIG_LAN966X_SWITCH) += lan966x-switch.o
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lan966x-switch-objs := lan966x_main.o
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lan966x-switch-objs := lan966x_main.o lan966x_phylink.o lan966x_port.o
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@@ -0,0 +1,173 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef __LAN966X_IFH_H__
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#define __LAN966X_IFH_H__
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/* Fields with description (*) should just be cleared upon injection
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* IFH is transmitted MSByte first (Highest bit pos sent as MSB of first byte)
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*/
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#define IFH_LEN 7
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/* Timestamp for frame */
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#define IFH_POS_TIMESTAMP 192
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/* Bypass analyzer with a prefilled IFH */
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#define IFH_POS_BYPASS 191
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/* Masqueraded injection with masq_port defining logical source port */
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#define IFH_POS_MASQ 190
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/* Masqueraded port number for injection */
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#define IFH_POS_MASQ_PORT 186
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/* Frame length (*) */
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#define IFH_POS_LEN 178
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/* Cell filling mode. Full(0),Etype(1), LlctOpt(2), Llct(3) */
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#define IFH_POS_WRDMODE 176
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/* Frame has 16 bits rtag removed compared to line data */
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#define IFH_POS_RTAG48 175
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/* Frame has a redundancy tag */
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#define IFH_POS_HAS_RED_TAG 174
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/* Frame has been cut through forwarded (*) */
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#define IFH_POS_CUTTHRU 173
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/* Rewriter command */
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#define IFH_POS_REW_CMD 163
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/* Enable OAM-related rewriting. PDU_TYPE encodes OAM type. */
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#define IFH_POS_REW_OAM 162
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/* PDU type. Encoding: (0-NONE, 1-Y1731_CCM, 2-MRP_TST, 3-MRP_ITST, 4-DLR_BCN,
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* 5-DLR_ADV, 6-RTE_NULL_INJ, 7-IPV4, 8-IPV6, 9-Y1731_NON_CCM).
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*/
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#define IFH_POS_PDU_TYPE 158
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/* Update FCS before transmission */
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#define IFH_POS_FCS_UPD 157
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/* Classified DSCP value of frame */
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#define IFH_POS_DSCP 151
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/* Yellow indication */
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#define IFH_POS_DP 150
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/* Process in RTE/inbound */
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#define IFH_POS_RTE_INB_UPDATE 149
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/* Number of tags to pop from frame */
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#define IFH_POS_POP_CNT 147
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/* Number of tags in front of the ethertype */
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#define IFH_POS_ETYPE_OFS 145
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/* Logical source port of frame (*) */
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#define IFH_POS_SRCPORT 141
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/* Sequence number in redundancy tag */
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#define IFH_POS_SEQ_NUM 120
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/* Stagd flag and classified TCI of frame (PCP/DEI/VID) */
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#define IFH_POS_TCI 103
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/* Classified internal priority for queuing */
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#define IFH_POS_QOS_CLASS 100
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/* Bit mask with eight cpu copy classses */
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#define IFH_POS_CPUQ 92
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/* Relearn + learn flags (*) */
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#define IFH_POS_LEARN_FLAGS 90
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/* SFLOW identifier for frame (0-8: Tx port, 9: Rx sampling, 15: No sampling) */
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#define IFH_POS_SFLOW_ID 86
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/* Set if an ACL/S2 rule was hit (*).
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* Super priority: acl_hit=0 and acl_hit(4)=1.
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*/
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#define IFH_POS_ACL_HIT 85
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/* S2 rule index hit (*) */
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#define IFH_POS_ACL_IDX 79
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/* ISDX as classified by S1 */
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#define IFH_POS_ISDX 71
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/* Destination ports for frame */
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#define IFH_POS_DSTS 62
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/* Storm policer to be applied: None/Uni/Multi/Broad (*) */
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#define IFH_POS_FLOOD 60
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/* Redundancy tag operation */
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#define IFH_POS_SEQ_OP 58
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/* Classified internal priority for resourcemgt, tagging etc */
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#define IFH_POS_IPV 55
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/* Frame is for AFI use */
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#define IFH_POS_AFI 54
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/* Internal aging value (*) */
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#define IFH_POS_AGED 52
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/* RTP Identifier */
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#define IFH_POS_RTP_ID 42
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/* RTP MRPD flow */
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#define IFH_POS_RTP_SUBID 41
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/* Profinet DataStatus or opcua GroupVersion MSB */
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#define IFH_POS_PN_DATA_STATUS 33
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/* Profinet transfer status (1 iff the status is 0) */
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#define IFH_POS_PN_TRANSF_STATUS_ZERO 32
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/* Profinet cycle counter or opcua NetworkMessageNumber */
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#define IFH_POS_PN_CC 16
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#define IFH_WID_TIMESTAMP 32
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#define IFH_WID_BYPASS 1
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#define IFH_WID_MASQ 1
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#define IFH_WID_MASQ_PORT 4
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#define IFH_WID_LEN 14
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#define IFH_WID_WRDMODE 2
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#define IFH_WID_RTAG48 1
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#define IFH_WID_HAS_RED_TAG 1
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#define IFH_WID_CUTTHRU 1
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#define IFH_WID_REW_CMD 10
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#define IFH_WID_REW_OAM 1
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#define IFH_WID_PDU_TYPE 4
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#define IFH_WID_FCS_UPD 1
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#define IFH_WID_DSCP 6
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#define IFH_WID_DP 1
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#define IFH_WID_RTE_INB_UPDATE 1
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#define IFH_WID_POP_CNT 2
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#define IFH_WID_ETYPE_OFS 2
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#define IFH_WID_SRCPORT 4
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#define IFH_WID_SEQ_NUM 16
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#define IFH_WID_TCI 17
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#define IFH_WID_QOS_CLASS 3
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#define IFH_WID_CPUQ 8
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#define IFH_WID_LEARN_FLAGS 2
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#define IFH_WID_SFLOW_ID 4
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#define IFH_WID_ACL_HIT 1
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#define IFH_WID_ACL_IDX 6
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#define IFH_WID_ISDX 8
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#define IFH_WID_DSTS 9
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#define IFH_WID_FLOOD 2
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#define IFH_WID_SEQ_OP 2
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#define IFH_WID_IPV 3
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#define IFH_WID_AFI 1
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#define IFH_WID_AGED 2
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#define IFH_WID_RTP_ID 10
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#define IFH_WID_RTP_SUBID 1
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#define IFH_WID_PN_DATA_STATUS 8
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#define IFH_WID_PN_TRANSF_STATUS_ZERO 1
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#define IFH_WID_PN_CC 16
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#endif /* __LAN966X_IFH_H__ */
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File diff suppressed because it is too large
Load Diff
@@ -3,7 +3,12 @@
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#ifndef __LAN966X_MAIN_H__
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#define __LAN966X_MAIN_H__
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#include <linux/etherdevice.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include "lan966x_regs.h"
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#include "lan966x_ifh.h"
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#define LAN966X_BUFFER_CELL_SZ 64
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#define LAN966X_BUFFER_MEMORY (160 * 1024)
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@@ -27,6 +32,7 @@
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#define PGID_MCIPV6 (PGID_AGGR - 1)
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#define LAN966X_SPEED_NONE 0
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#define LAN966X_SPEED_2500 1
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#define LAN966X_SPEED_1000 1
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#define LAN966X_SPEED_100 2
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#define LAN966X_SPEED_10 3
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@@ -44,15 +50,47 @@ struct lan966x {
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void __iomem *regs[NUM_TARGETS];
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int shared_queue_sz;
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/* interrupts */
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int xtr_irq;
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};
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struct lan966x_port_config {
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phy_interface_t portmode;
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const unsigned long *advertising;
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int speed;
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int duplex;
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u32 pause;
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bool inband;
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bool autoneg;
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};
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struct lan966x_port {
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struct net_device *dev;
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struct lan966x *lan966x;
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u8 chip_port;
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u16 pvid;
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struct phylink_config phylink_config;
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struct phylink_pcs phylink_pcs;
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struct lan966x_port_config config;
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struct phylink *phylink;
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struct phy *serdes;
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struct fwnode_handle *fwnode;
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};
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extern const struct phylink_mac_ops lan966x_phylink_mac_ops;
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extern const struct phylink_pcs_ops lan966x_phylink_pcs_ops;
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void lan966x_port_config_down(struct lan966x_port *port);
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void lan966x_port_config_up(struct lan966x_port *port);
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void lan966x_port_status_get(struct lan966x_port *port,
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struct phylink_link_state *state);
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int lan966x_port_pcs_set(struct lan966x_port *port,
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struct lan966x_port_config *config);
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void lan966x_port_init(struct lan966x_port *port);
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static inline void __iomem *lan_addr(void __iomem *base[],
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int id, int tinst, int tcnt,
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int gbase, int ginst,
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@@ -0,0 +1,127 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/module.h>
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#include <linux/phylink.h>
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#include <linux/device.h>
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#include <linux/netdevice.h>
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#include <linux/phy/phy.h>
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#include <linux/sfp.h>
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#include "lan966x_main.h"
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static void lan966x_phylink_mac_config(struct phylink_config *config,
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unsigned int mode,
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const struct phylink_link_state *state)
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{
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}
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static int lan966x_phylink_mac_prepare(struct phylink_config *config,
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unsigned int mode,
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phy_interface_t iface)
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{
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struct lan966x_port *port = netdev_priv(to_net_dev(config->dev));
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int err;
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if (port->serdes) {
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err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET,
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iface);
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if (err) {
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netdev_err(to_net_dev(config->dev),
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"Could not set mode of SerDes\n");
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return err;
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}
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}
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return 0;
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}
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static void lan966x_phylink_mac_link_up(struct phylink_config *config,
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struct phy_device *phy,
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unsigned int mode,
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phy_interface_t interface,
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int speed, int duplex,
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bool tx_pause, bool rx_pause)
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{
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struct lan966x_port *port = netdev_priv(to_net_dev(config->dev));
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struct lan966x_port_config *port_config = &port->config;
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port_config->duplex = duplex;
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port_config->speed = speed;
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port_config->pause = 0;
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port_config->pause |= tx_pause ? MLO_PAUSE_TX : 0;
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port_config->pause |= rx_pause ? MLO_PAUSE_RX : 0;
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lan966x_port_config_up(port);
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}
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static void lan966x_phylink_mac_link_down(struct phylink_config *config,
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unsigned int mode,
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phy_interface_t interface)
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{
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struct lan966x_port *port = netdev_priv(to_net_dev(config->dev));
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struct lan966x *lan966x = port->lan966x;
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lan966x_port_config_down(port);
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/* Take PCS out of reset */
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lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
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DEV_CLOCK_CFG_PCS_TX_RST_SET(0),
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DEV_CLOCK_CFG_PCS_RX_RST |
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DEV_CLOCK_CFG_PCS_TX_RST,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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}
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static struct lan966x_port *lan966x_pcs_to_port(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct lan966x_port, phylink_pcs);
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}
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static void lan966x_pcs_get_state(struct phylink_pcs *pcs,
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struct phylink_link_state *state)
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{
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struct lan966x_port *port = lan966x_pcs_to_port(pcs);
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lan966x_port_status_get(port, state);
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}
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static int lan966x_pcs_config(struct phylink_pcs *pcs,
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unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct lan966x_port *port = lan966x_pcs_to_port(pcs);
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struct lan966x_port_config config;
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int ret;
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config = port->config;
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config.portmode = interface;
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config.inband = phylink_autoneg_inband(mode);
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config.autoneg = phylink_test(advertising, Autoneg);
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config.advertising = advertising;
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ret = lan966x_port_pcs_set(port, &config);
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if (ret)
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netdev_err(port->dev, "port PCS config failed: %d\n", ret);
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return ret;
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}
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static void lan966x_pcs_aneg_restart(struct phylink_pcs *pcs)
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{
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/* Currently not used */
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}
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const struct phylink_mac_ops lan966x_phylink_mac_ops = {
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.validate = phylink_generic_validate,
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.mac_config = lan966x_phylink_mac_config,
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.mac_prepare = lan966x_phylink_mac_prepare,
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.mac_link_down = lan966x_phylink_mac_link_down,
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.mac_link_up = lan966x_phylink_mac_link_up,
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};
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const struct phylink_pcs_ops lan966x_phylink_pcs_ops = {
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.pcs_get_state = lan966x_pcs_get_state,
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.pcs_config = lan966x_pcs_config,
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.pcs_an_restart = lan966x_pcs_aneg_restart,
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};
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@@ -0,0 +1,412 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/netdevice.h>
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#include <linux/phy/phy.h>
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#include "lan966x_main.h"
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/* Watermark encode */
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#define MULTIPLIER_BIT BIT(8)
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static u32 lan966x_wm_enc(u32 value)
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{
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value /= LAN966X_BUFFER_CELL_SZ;
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if (value >= MULTIPLIER_BIT) {
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value /= 16;
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if (value >= MULTIPLIER_BIT)
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value = (MULTIPLIER_BIT - 1);
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value |= MULTIPLIER_BIT;
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}
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return value;
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}
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static void lan966x_port_link_down(struct lan966x_port *port)
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{
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struct lan966x *lan966x = port->lan966x;
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u32 val, delay = 0;
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/* 0.5: Disable any AFI */
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lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(1) |
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AFI_PORT_CFG_FRM_OUT_MAX_SET(0),
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AFI_PORT_CFG_FC_SKIP_TTI_INJ |
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AFI_PORT_CFG_FRM_OUT_MAX,
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lan966x, AFI_PORT_CFG(port->chip_port));
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/* wait for reg afi_port_frm_out to become 0 for the port */
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while (true) {
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val = lan_rd(lan966x, AFI_PORT_FRM_OUT(port->chip_port));
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if (!AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(val))
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break;
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usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
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delay++;
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if (delay == 2000) {
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pr_err("AFI timeout chip port %u", port->chip_port);
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break;
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}
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}
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delay = 0;
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/* 1: Reset the PCS Rx clock domain */
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lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(1),
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DEV_CLOCK_CFG_PCS_RX_RST,
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lan966x, DEV_CLOCK_CFG(port->chip_port));
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/* 2: Disable MAC frame reception */
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lan_rmw(DEV_MAC_ENA_CFG_RX_ENA_SET(0),
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DEV_MAC_ENA_CFG_RX_ENA,
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lan966x, DEV_MAC_ENA_CFG(port->chip_port));
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/* 3: Disable traffic being sent to or from switch port */
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lan_rmw(QSYS_SW_PORT_MODE_PORT_ENA_SET(0),
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QSYS_SW_PORT_MODE_PORT_ENA,
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lan966x, QSYS_SW_PORT_MODE(port->chip_port));
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/* 4: Disable dequeuing from the egress queues */
|
||||
lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(1),
|
||||
QSYS_PORT_MODE_DEQUEUE_DIS,
|
||||
lan966x, QSYS_PORT_MODE(port->chip_port));
|
||||
|
||||
/* 5: Disable Flowcontrol */
|
||||
lan_rmw(SYS_PAUSE_CFG_PAUSE_ENA_SET(0),
|
||||
SYS_PAUSE_CFG_PAUSE_ENA,
|
||||
lan966x, SYS_PAUSE_CFG(port->chip_port));
|
||||
|
||||
/* 5.1: Disable PFC */
|
||||
lan_rmw(QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(0),
|
||||
QSYS_SW_PORT_MODE_TX_PFC_ENA,
|
||||
lan966x, QSYS_SW_PORT_MODE(port->chip_port));
|
||||
|
||||
/* 6: Wait a worst case time 8ms (jumbo/10Mbit) */
|
||||
usleep_range(8 * USEC_PER_MSEC, 9 * USEC_PER_MSEC);
|
||||
|
||||
/* 7: Disable HDX backpressure */
|
||||
lan_rmw(SYS_FRONT_PORT_MODE_HDX_MODE_SET(0),
|
||||
SYS_FRONT_PORT_MODE_HDX_MODE,
|
||||
lan966x, SYS_FRONT_PORT_MODE(port->chip_port));
|
||||
|
||||
/* 8: Flush the queues accociated with the port */
|
||||
lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(3),
|
||||
QSYS_SW_PORT_MODE_AGING_MODE,
|
||||
lan966x, QSYS_SW_PORT_MODE(port->chip_port));
|
||||
|
||||
/* 9: Enable dequeuing from the egress queues */
|
||||
lan_rmw(QSYS_PORT_MODE_DEQUEUE_DIS_SET(0),
|
||||
QSYS_PORT_MODE_DEQUEUE_DIS,
|
||||
lan966x, QSYS_PORT_MODE(port->chip_port));
|
||||
|
||||
/* 10: Wait until flushing is complete */
|
||||
while (true) {
|
||||
val = lan_rd(lan966x, QSYS_SW_STATUS(port->chip_port));
|
||||
if (!QSYS_SW_STATUS_EQ_AVAIL_GET(val))
|
||||
break;
|
||||
|
||||
usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
|
||||
delay++;
|
||||
if (delay == 2000) {
|
||||
pr_err("Flush timeout chip port %u", port->chip_port);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* 11: Reset the Port and MAC clock domains */
|
||||
lan_rmw(DEV_MAC_ENA_CFG_TX_ENA_SET(0),
|
||||
DEV_MAC_ENA_CFG_TX_ENA,
|
||||
lan966x, DEV_MAC_ENA_CFG(port->chip_port));
|
||||
|
||||
lan_rmw(DEV_CLOCK_CFG_PORT_RST_SET(1),
|
||||
DEV_CLOCK_CFG_PORT_RST,
|
||||
lan966x, DEV_CLOCK_CFG(port->chip_port));
|
||||
|
||||
usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
|
||||
|
||||
lan_rmw(DEV_CLOCK_CFG_MAC_TX_RST_SET(1) |
|
||||
DEV_CLOCK_CFG_MAC_RX_RST_SET(1) |
|
||||
DEV_CLOCK_CFG_PORT_RST_SET(1),
|
||||
DEV_CLOCK_CFG_MAC_TX_RST |
|
||||
DEV_CLOCK_CFG_MAC_RX_RST |
|
||||
DEV_CLOCK_CFG_PORT_RST,
|
||||
lan966x, DEV_CLOCK_CFG(port->chip_port));
|
||||
|
||||
/* 12: Clear flushing */
|
||||
lan_rmw(QSYS_SW_PORT_MODE_AGING_MODE_SET(2),
|
||||
QSYS_SW_PORT_MODE_AGING_MODE,
|
||||
lan966x, QSYS_SW_PORT_MODE(port->chip_port));
|
||||
|
||||
/* The port is disabled and flushed, now set up the port in the
|
||||
* new operating mode
|
||||
*/
|
||||
}
|
||||
|
||||
static void lan966x_port_link_up(struct lan966x_port *port)
|
||||
{
|
||||
struct lan966x_port_config *config = &port->config;
|
||||
struct lan966x *lan966x = port->lan966x;
|
||||
int speed = 0, mode = 0;
|
||||
int atop_wm = 0;
|
||||
|
||||
switch (config->speed) {
|
||||
case SPEED_10:
|
||||
speed = LAN966X_SPEED_10;
|
||||
break;
|
||||
case SPEED_100:
|
||||
speed = LAN966X_SPEED_100;
|
||||
break;
|
||||
case SPEED_1000:
|
||||
speed = LAN966X_SPEED_1000;
|
||||
mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);
|
||||
break;
|
||||
case SPEED_2500:
|
||||
speed = LAN966X_SPEED_2500;
|
||||
mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Also the GIGA_MODE_ENA(1) needs to be set regardless of the
|
||||
* port speed for QSGMII ports.
|
||||
*/
|
||||
if (config->portmode == PHY_INTERFACE_MODE_QSGMII)
|
||||
mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(1);
|
||||
|
||||
lan_wr(config->duplex | mode,
|
||||
lan966x, DEV_MAC_MODE_CFG(port->chip_port));
|
||||
|
||||
lan_rmw(DEV_MAC_IFG_CFG_TX_IFG_SET(config->duplex ? 6 : 5) |
|
||||
DEV_MAC_IFG_CFG_RX_IFG1_SET(config->speed == SPEED_10 ? 2 : 1) |
|
||||
DEV_MAC_IFG_CFG_RX_IFG2_SET(2),
|
||||
DEV_MAC_IFG_CFG_TX_IFG |
|
||||
DEV_MAC_IFG_CFG_RX_IFG1 |
|
||||
DEV_MAC_IFG_CFG_RX_IFG2,
|
||||
lan966x, DEV_MAC_IFG_CFG(port->chip_port));
|
||||
|
||||
lan_rmw(DEV_MAC_HDX_CFG_SEED_SET(4) |
|
||||
DEV_MAC_HDX_CFG_SEED_LOAD_SET(1),
|
||||
DEV_MAC_HDX_CFG_SEED |
|
||||
DEV_MAC_HDX_CFG_SEED_LOAD,
|
||||
lan966x, DEV_MAC_HDX_CFG(port->chip_port));
|
||||
|
||||
if (config->portmode == PHY_INTERFACE_MODE_GMII) {
|
||||
if (config->speed == SPEED_1000)
|
||||
lan_rmw(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(1),
|
||||
CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA,
|
||||
lan966x,
|
||||
CHIP_TOP_CUPHY_PORT_CFG(port->chip_port));
|
||||
else
|
||||
lan_rmw(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(0),
|
||||
CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA,
|
||||
lan966x,
|
||||
CHIP_TOP_CUPHY_PORT_CFG(port->chip_port));
|
||||
}
|
||||
|
||||
/* No PFC */
|
||||
lan_wr(ANA_PFC_CFG_FC_LINK_SPEED_SET(speed),
|
||||
lan966x, ANA_PFC_CFG(port->chip_port));
|
||||
|
||||
lan_rmw(DEV_PCS1G_CFG_PCS_ENA_SET(1),
|
||||
DEV_PCS1G_CFG_PCS_ENA,
|
||||
lan966x, DEV_PCS1G_CFG(port->chip_port));
|
||||
|
||||
lan_rmw(DEV_PCS1G_SD_CFG_SD_ENA_SET(0),
|
||||
DEV_PCS1G_SD_CFG_SD_ENA,
|
||||
lan966x, DEV_PCS1G_SD_CFG(port->chip_port));
|
||||
|
||||
/* Set Pause WM hysteresis, start/stop are in 1518 byte units */
|
||||
lan_wr(SYS_PAUSE_CFG_PAUSE_ENA_SET(1) |
|
||||
SYS_PAUSE_CFG_PAUSE_STOP_SET(lan966x_wm_enc(4 * 1518)) |
|
||||
SYS_PAUSE_CFG_PAUSE_START_SET(lan966x_wm_enc(6 * 1518)),
|
||||
lan966x, SYS_PAUSE_CFG(port->chip_port));
|
||||
|
||||
/* Set SMAC of Pause frame (00:00:00:00:00:00) */
|
||||
lan_wr(0, lan966x, DEV_FC_MAC_LOW_CFG(port->chip_port));
|
||||
lan_wr(0, lan966x, DEV_FC_MAC_HIGH_CFG(port->chip_port));
|
||||
|
||||
/* Flow control */
|
||||
lan_rmw(SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(speed) |
|
||||
SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(7) |
|
||||
SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(1) |
|
||||
SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(0xffff) |
|
||||
SYS_MAC_FC_CFG_RX_FC_ENA_SET(config->pause & MLO_PAUSE_RX ? 1 : 0) |
|
||||
SYS_MAC_FC_CFG_TX_FC_ENA_SET(config->pause & MLO_PAUSE_TX ? 1 : 0),
|
||||
SYS_MAC_FC_CFG_FC_LINK_SPEED |
|
||||
SYS_MAC_FC_CFG_FC_LATENCY_CFG |
|
||||
SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
|
||||
SYS_MAC_FC_CFG_PAUSE_VAL_CFG |
|
||||
SYS_MAC_FC_CFG_RX_FC_ENA |
|
||||
SYS_MAC_FC_CFG_TX_FC_ENA,
|
||||
lan966x, SYS_MAC_FC_CFG(port->chip_port));
|
||||
|
||||
/* Tail dropping watermark */
|
||||
atop_wm = lan966x->shared_queue_sz;
|
||||
|
||||
/* The total memory size is diveded by number of front ports plus CPU
|
||||
* port
|
||||
*/
|
||||
lan_wr(lan966x_wm_enc(atop_wm / lan966x->num_phys_ports + 1), lan966x,
|
||||
SYS_ATOP(port->chip_port));
|
||||
lan_wr(lan966x_wm_enc(atop_wm), lan966x, SYS_ATOP_TOT_CFG);
|
||||
|
||||
/* This needs to be at the end */
|
||||
/* Enable MAC module */
|
||||
lan_wr(DEV_MAC_ENA_CFG_RX_ENA_SET(1) |
|
||||
DEV_MAC_ENA_CFG_TX_ENA_SET(1),
|
||||
lan966x, DEV_MAC_ENA_CFG(port->chip_port));
|
||||
|
||||
/* Take out the clock from reset */
|
||||
lan_wr(DEV_CLOCK_CFG_LINK_SPEED_SET(speed),
|
||||
lan966x, DEV_CLOCK_CFG(port->chip_port));
|
||||
|
||||
/* Core: Enable port for frame transfer */
|
||||
lan_wr(QSYS_SW_PORT_MODE_PORT_ENA_SET(1) |
|
||||
QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(1) |
|
||||
QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(1),
|
||||
lan966x, QSYS_SW_PORT_MODE(port->chip_port));
|
||||
|
||||
lan_rmw(AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(0) |
|
||||
AFI_PORT_CFG_FRM_OUT_MAX_SET(16),
|
||||
AFI_PORT_CFG_FC_SKIP_TTI_INJ |
|
||||
AFI_PORT_CFG_FRM_OUT_MAX,
|
||||
lan966x, AFI_PORT_CFG(port->chip_port));
|
||||
}
|
||||
|
||||
void lan966x_port_config_down(struct lan966x_port *port)
|
||||
{
|
||||
lan966x_port_link_down(port);
|
||||
}
|
||||
|
||||
void lan966x_port_config_up(struct lan966x_port *port)
|
||||
{
|
||||
lan966x_port_link_up(port);
|
||||
}
|
||||
|
||||
void lan966x_port_status_get(struct lan966x_port *port,
|
||||
struct phylink_link_state *state)
|
||||
{
|
||||
struct lan966x *lan966x = port->lan966x;
|
||||
bool link_down;
|
||||
u16 bmsr = 0;
|
||||
u16 lp_adv;
|
||||
u32 val;
|
||||
|
||||
val = lan_rd(lan966x, DEV_PCS1G_STICKY(port->chip_port));
|
||||
link_down = DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(val);
|
||||
if (link_down)
|
||||
lan_wr(val, lan966x, DEV_PCS1G_STICKY(port->chip_port));
|
||||
|
||||
/* Get both current Link and Sync status */
|
||||
val = lan_rd(lan966x, DEV_PCS1G_LINK_STATUS(port->chip_port));
|
||||
state->link = DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(val) &&
|
||||
DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(val);
|
||||
state->link &= !link_down;
|
||||
|
||||
/* Get PCS ANEG status register */
|
||||
val = lan_rd(lan966x, DEV_PCS1G_ANEG_STATUS(port->chip_port));
|
||||
/* Aneg complete provides more information */
|
||||
if (DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(val)) {
|
||||
state->an_complete = true;
|
||||
|
||||
bmsr |= state->link ? BMSR_LSTATUS : 0;
|
||||
bmsr |= BMSR_ANEGCOMPLETE;
|
||||
|
||||
lp_adv = DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(val);
|
||||
phylink_mii_c22_pcs_decode_state(state, bmsr, lp_adv);
|
||||
} else {
|
||||
if (!state->link)
|
||||
return;
|
||||
|
||||
if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
|
||||
state->speed = SPEED_1000;
|
||||
else if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
|
||||
state->speed = SPEED_2500;
|
||||
|
||||
state->duplex = DUPLEX_FULL;
|
||||
}
|
||||
}
|
||||
|
||||
int lan966x_port_pcs_set(struct lan966x_port *port,
|
||||
struct lan966x_port_config *config)
|
||||
{
|
||||
struct lan966x *lan966x = port->lan966x;
|
||||
bool inband_aneg = false;
|
||||
bool outband;
|
||||
int err;
|
||||
|
||||
if (config->inband) {
|
||||
if (config->portmode == PHY_INTERFACE_MODE_SGMII ||
|
||||
config->portmode == PHY_INTERFACE_MODE_QSGMII)
|
||||
inband_aneg = true; /* Cisco-SGMII in-band-aneg */
|
||||
else if (config->portmode == PHY_INTERFACE_MODE_1000BASEX &&
|
||||
config->autoneg)
|
||||
inband_aneg = true; /* Clause-37 in-band-aneg */
|
||||
|
||||
if (config->speed > 0) {
|
||||
err = phy_set_speed(port->serdes, config->speed);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
outband = false;
|
||||
} else {
|
||||
outband = true;
|
||||
}
|
||||
|
||||
/* Disable or enable inband */
|
||||
lan_rmw(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(outband),
|
||||
DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA,
|
||||
lan966x, DEV_PCS1G_MODE_CFG(port->chip_port));
|
||||
|
||||
/* Enable PCS */
|
||||
lan_wr(DEV_PCS1G_CFG_PCS_ENA_SET(1),
|
||||
lan966x, DEV_PCS1G_CFG(port->chip_port));
|
||||
|
||||
if (inband_aneg) {
|
||||
int adv = phylink_mii_c22_pcs_encode_advertisement(config->portmode,
|
||||
config->advertising);
|
||||
if (adv >= 0)
|
||||
/* Enable in-band aneg */
|
||||
lan_wr(DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(adv) |
|
||||
DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(1) |
|
||||
DEV_PCS1G_ANEG_CFG_ENA_SET(1) |
|
||||
DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(1),
|
||||
lan966x, DEV_PCS1G_ANEG_CFG(port->chip_port));
|
||||
} else {
|
||||
lan_wr(0, lan966x, DEV_PCS1G_ANEG_CFG(port->chip_port));
|
||||
}
|
||||
|
||||
/* Take PCS out of reset */
|
||||
lan_rmw(DEV_CLOCK_CFG_LINK_SPEED_SET(2) |
|
||||
DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
|
||||
DEV_CLOCK_CFG_PCS_TX_RST_SET(0),
|
||||
DEV_CLOCK_CFG_LINK_SPEED |
|
||||
DEV_CLOCK_CFG_PCS_RX_RST |
|
||||
DEV_CLOCK_CFG_PCS_TX_RST,
|
||||
lan966x, DEV_CLOCK_CFG(port->chip_port));
|
||||
|
||||
port->config = *config;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void lan966x_port_init(struct lan966x_port *port)
|
||||
{
|
||||
struct lan966x_port_config *config = &port->config;
|
||||
struct lan966x *lan966x = port->lan966x;
|
||||
|
||||
lan_rmw(ANA_PORT_CFG_LEARN_ENA_SET(0),
|
||||
ANA_PORT_CFG_LEARN_ENA,
|
||||
lan966x, ANA_PORT_CFG(port->chip_port));
|
||||
|
||||
lan966x_port_config_down(port);
|
||||
|
||||
if (config->portmode != PHY_INTERFACE_MODE_QSGMII)
|
||||
return;
|
||||
|
||||
lan_rmw(DEV_CLOCK_CFG_PCS_RX_RST_SET(0) |
|
||||
DEV_CLOCK_CFG_PCS_TX_RST_SET(0) |
|
||||
DEV_CLOCK_CFG_LINK_SPEED_SET(LAN966X_SPEED_1000),
|
||||
DEV_CLOCK_CFG_PCS_RX_RST |
|
||||
DEV_CLOCK_CFG_PCS_TX_RST |
|
||||
DEV_CLOCK_CFG_LINK_SPEED,
|
||||
lan966x, DEV_CLOCK_CFG(port->chip_port));
|
||||
}
|
||||
Reference in New Issue
Block a user