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staging: comedi: addi_apci_1500: rewrite the subdevice support functions
This driver is a mess. It violates the comedi API so much that I doubt anything actually works. Drop the addi-data/hwdrv_apci1500.c file and rewrite the subdevice support functions. This board has 16 digital inputs (subdevice 0) and 16 digital outputs (subdevice 1). It also has three 16-bit timer/counters provided by a Z8536 CIO chip (subdevice 2). The Z8536 chip is also used to support pattern match interrupt detection of the first 14 digital input channels. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
53c0bee80f
commit
a8c66b684e
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/*
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* Z8536 CIO Internal registers
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*/
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#ifndef _Z8536_H
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#define _Z8536_H
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/* Master Interrupt Control register */
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#define Z8536_INT_CTRL_REG 0x00
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#define Z8536_INT_CTRL_MIE BIT(7) /* Master Interrupt Enable */
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#define Z8536_INT_CTRL_DLC BIT(6) /* Disable Lower Chain */
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#define Z8536_INT_CTRL_NV BIT(5) /* No Vector */
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#define Z8536_INT_CTRL_PA_VIS BIT(4) /* Port A Vect Inc Status */
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#define Z8536_INT_CTRL_PB_VIS BIT(3) /* Port B Vect Inc Status */
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#define Z8536_INT_CTRL_VT_VIS BIT(2) /* C/T Vect Inc Status */
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#define Z8536_INT_CTRL_RJA BIT(1) /* Right Justified Addresses */
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#define Z8536_INT_CTRL_RESET BIT(0) /* Reset */
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/* Master Configuration Control register */
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#define Z8536_CFG_CTRL_REG 0x01
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#define Z8536_CFG_CTRL_PBE BIT(7) /* Port B Enable */
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#define Z8536_CFG_CTRL_CT1E BIT(6) /* C/T 1 Enable */
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#define Z8536_CFG_CTRL_CT2E BIT(5) /* C/T 2 Enable */
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#define Z8536_CFG_CTRL_PCE_CT3E BIT(4) /* Port C & C/T 3 Enable */
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#define Z8536_CFG_CTRL_PLC BIT(3) /* Port A/B Link Control */
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#define Z8536_CFG_CTRL_PAE BIT(2) /* Port A Enable */
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#define Z8536_CFG_CTRL_LC_INDEP (0 << 0)/* C/Ts Independent */
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#define Z8536_CFG_CTRL_LC_GATE (1 << 0)/* C/T 1 Out Gates C/T 2 */
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#define Z8536_CFG_CTRL_LC_TRIG (2 << 0)/* C/T 1 Out Triggers C/T 2 */
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#define Z8536_CFG_CTRL_LC_CLK (3 << 0)/* C/T 1 Out Clocks C/T 2 */
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#define Z8536_CFG_CTRL_LC_MASK (3 << 0)/* C/T Link Control mask */
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/* Interrupt Vector registers */
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#define Z8536_PA_INT_VECT_REG 0x02
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#define Z8536_PB_INT_VECT_REG 0x03
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#define Z8536_CT_INT_VECT_REG 0x04
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#define Z8536_CURR_INT_VECT_REG 0x1f
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/* Port A/B & Counter/Timer 1/2/3 Command and Status registers */
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#define Z8536_PA_CMDSTAT_REG 0x08
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#define Z8536_PB_CMDSTAT_REG 0x09
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#define Z8536_CT1_CMDSTAT_REG 0x0a
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#define Z8536_CT2_CMDSTAT_REG 0x0b
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#define Z8536_CT3_CMDSTAT_REG 0x0c
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#define Z8536_CT_CMDSTAT_REG(x) (0x0a + (x))
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#define Z8536_CMD_NULL (0 << 5)/* Null Code */
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#define Z8536_CMD_CLR_IP_IUS (1 << 5)/* Clear IP & IUS */
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#define Z8536_CMD_SET_IUS (2 << 5)/* Set IUS */
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#define Z8536_CMD_CLR_IUS (3 << 5)/* Clear IUS */
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#define Z8536_CMD_SET_IP (4 << 5)/* Set IP */
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#define Z8536_CMD_CLR_IP (5 << 5)/* Clear IP */
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#define Z8536_CMD_SET_IE (6 << 5)/* Set IE */
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#define Z8536_CMD_CLR_IE (7 << 5)/* Clear IE */
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#define Z8536_CMD_MASK (7 << 5)
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#define Z8536_STAT_IUS BIT(7) /* Interrupt Under Service */
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#define Z8536_STAT_IE BIT(6) /* Interrupt Enable */
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#define Z8536_STAT_IP BIT(5) /* Interrupt Pending */
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#define Z8536_STAT_ERR BIT(4) /* Interrupt Error */
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#define Z8536_STAT_IE_IP (Z8536_STAT_IE | Z8536_STAT_IP)
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#define Z8536_PAB_STAT_ORE BIT(3) /* Output Register Empty */
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#define Z8536_PAB_STAT_IRF BIT(2) /* Input Register Full */
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#define Z8536_PAB_STAT_PMF BIT(1) /* Pattern Match Flag */
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#define Z8536_PAB_CMDSTAT_IOE BIT(0) /* Interrupt On Error */
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#define Z8536_CT_CMD_RCC BIT(3) /* Read Counter Control */
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#define Z8536_CT_CMDSTAT_GCB BIT(2) /* Gate Command Bit */
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#define Z8536_CT_CMD_TCB BIT(1) /* Trigger Command Bit */
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#define Z8536_CT_STAT_CIP BIT(0) /* Count In Progress */
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/* Port Data registers */
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#define Z8536_PA_DATA_REG 0x0d
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#define Z8536_PB_DATA_REG 0x0e
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#define Z8536_PC_DATA_REG 0x0f
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/* Counter/Timer 1/2/3 Current Count registers */
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#define Z8536_CT1_VAL_MSB_REG 0x10
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#define Z8536_CT1_VAL_LSB_REG 0x11
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#define Z8536_CT2_VAL_MSB_REG 0x12
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#define Z8536_CT2_VAL_LSB_REG 0x13
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#define Z8536_CT3_VAL_MSB_REG 0x14
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#define Z8536_CT3_VAL_LSB_REG 0x15
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#define Z8536_CT_VAL_MSB_REG(x) (0x10 + ((x) * 2))
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#define Z8536_CT_VAL_LSB_REG(x) (0x11 + ((x) * 2))
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/* Counter/Timer 1/2/3 Time Constant registers */
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#define Z8536_CT1_RELOAD_MSB_REG 0x16
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#define Z8536_CT1_RELOAD_LSB_REG 0x17
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#define Z8536_CT2_RELOAD_MSB_REG 0x18
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#define Z8536_CT2_RELOAD_LSB_REG 0x19
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#define Z8536_CT3_RELOAD_MSB_REG 0x1a
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#define Z8536_CT3_RELOAD_LSB_REG 0x1b
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#define Z8536_CT_RELOAD_MSB_REG(x) (0x16 + ((x) * 2))
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#define Z8536_CT_RELOAD_LSB_REG(x) (0x17 + ((x) * 2))
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/* Counter/Timer 1/2/3 Mode Specification registers */
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#define Z8536_CT1_MODE_REG 0x1c
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#define Z8536_CT2_MODE_REG 0x1d
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#define Z8536_CT3_MODE_REG 0x1e
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#define Z8536_CT_MODE_REG(x) (0x1c + (x))
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#define Z8536_CT_MODE_CSC BIT(7) /* Continuous/Single Cycle */
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#define Z8536_CT_MODE_EOE BIT(6) /* External Output Enable */
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#define Z8536_CT_MODE_ECE BIT(5) /* External Count Enable */
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#define Z8536_CT_MODE_ETE BIT(4) /* External Trigger Enable */
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#define Z8536_CT_MODE_EGE BIT(3) /* External Gate Enable */
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#define Z8536_CT_MODE_REB BIT(2) /* Retrigger Enable Bit */
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#define Z8536_CT_MODE_DCS_PULSE (0 << 0)/* Duty Cycle - Pulse */
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#define Z8536_CT_MODE_DCS_ONESHOT (1 << 0)/* Duty Cycle - One-Shot */
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#define Z8536_CT_MODE_DCS_SQRWAVE (2 << 0)/* Duty Cycle - Square Wave */
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#define Z8536_CT_MODE_DCS_DO_NOT_USE (3 << 0)/* Duty Cycle - Do Not Use */
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#define Z8536_CT_MODE_DCS_MASK (3 << 0)/* Duty Cycle mask */
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/* Port A/B Mode Specification registers */
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#define Z8536_PA_MODE_REG 0x20
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#define Z8536_PB_MODE_REG 0x28
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#define Z8536_PAB_MODE_PTS_BIT (0 << 6)/* Bit Port */
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#define Z8536_PAB_MODE_PTS_INPUT (1 << 6)/* Input Port */
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#define Z8536_PAB_MODE_PTS_OUTPUT (2 << 6)/* Output Port */
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#define Z8536_PAB_MODE_PTS_BIDIR (3 << 6)/* Bidirectional Port */
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#define Z8536_PAB_MODE_PTS_MASK (3 << 6)/* Port Type Select mask */
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#define Z8536_PAB_MODE_ITB BIT(5) /* Interrupt on Two Bytes */
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#define Z8536_PAB_MODE_SB BIT(4) /* Single Buffered mode */
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#define Z8536_PAB_MODE_IMO BIT(3) /* Interrupt on Match Only */
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#define Z8536_PAB_MODE_PMS_DISABLE (0 << 1)/* Disable Pattern Match */
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#define Z8536_PAB_MODE_PMS_AND (1 << 1)/* "AND" mode */
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#define Z8536_PAB_MODE_PMS_OR (2 << 1)/* "OR" mode */
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#define Z8536_PAB_MODE_PMS_OR_PEV (3 << 1)/* "OR-Priority" mode */
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#define Z8536_PAB_MODE_PMS_MASK (3 << 1)/* Pattern Mode mask */
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#define Z8536_PAB_MODE_LPM BIT(0) /* Latch on Pattern Match */
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#define Z8536_PAB_MODE_DTE BIT(0) /* Deskew Timer Enabled */
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/* Port A/B Handshake Specification registers */
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#define Z8536_PA_HANDSHAKE_REG 0x21
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#define Z8536_PB_HANDSHAKE_REG 0x29
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#define Z8536_PAB_HANDSHAKE_HST_INTER (0 << 6)/* Interlocked Handshake */
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#define Z8536_PAB_HANDSHAKE_HST_STROBED (1 << 6)/* Strobed Handshake */
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#define Z8536_PAB_HANDSHAKE_HST_PULSED (2 << 6)/* Pulsed Handshake */
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#define Z8536_PAB_HANDSHAKE_HST_3WIRE (3 << 6)/* Three-Wire Handshake */
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#define Z8536_PAB_HANDSHAKE_HST_MASK (3 << 6)/* Handshake Type mask */
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#define Z8536_PAB_HANDSHAKE_RWS_DISABLE (0 << 3)/* Req/Wait Disabled */
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#define Z8536_PAB_HANDSHAKE_RWS_OUTWAIT (1 << 3)/* Output Wait */
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#define Z8536_PAB_HANDSHAKE_RWS_INWAIT (3 << 3)/* Input Wait */
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#define Z8536_PAB_HANDSHAKE_RWS_SPREQ (4 << 3)/* Special Request */
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#define Z8536_PAB_HANDSHAKE_RWS_OUTREQ (5 << 4)/* Output Request */
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#define Z8536_PAB_HANDSHAKE_RWS_INREQ (7 << 3)/* Input Request */
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#define Z8536_PAB_HANDSHAKE_RWS_MASK (7 << 3)/* Req/Wait mask */
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#define Z8536_PAB_HANDSHAKE_DESKEW(x) ((x) << 0)/* Deskew Time */
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#define Z8536_PAB_HANDSHAKE_DESKEW_MASK (3 << 0)/* Deskew Time mask */
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/*
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* Port A/B/C Data Path Polarity registers
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*
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* 0 = Non-Inverting
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* 1 = Inverting
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*/
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#define Z8536_PA_DPP_REG 0x22
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#define Z8536_PB_DPP_REG 0x2a
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#define Z8536_PC_DPP_REG 0x05
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/*
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* Port A/B/C Data Direction registers
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*
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* 0 = Output bit
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* 1 = Input bit
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*/
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#define Z8536_PA_DD_REG 0x23
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#define Z8536_PB_DD_REG 0x2b
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#define Z8536_PC_DD_REG 0x06
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/*
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* Port A/B/C Special I/O Control registers
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*
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* 0 = Normal Input or Output
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* 1 = Output with open drain or Input with 1's catcher
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*/
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#define Z8536_PA_SIO_REG 0x24
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#define Z8536_PB_SIO_REG 0x2c
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#define Z8536_PC_SIO_REG 0x07
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/*
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* Port A/B Pattern Polarity/Transition/Mask registers
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*
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* PM PT PP Pattern Specification
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* -- -- -- -------------------------------------
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* 0 0 x Bit masked off
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* 0 1 x Any transition
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* 1 0 0 Zero (low-level)
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* 1 0 1 One (high-level)
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* 1 1 0 One-to-zero transition (falling-edge)
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* 1 1 1 Zero-to-one transition (rising-edge)
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*/
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#define Z8536_PA_PP_REG 0x25
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#define Z8536_PB_PP_REG 0x2d
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#define Z8536_PA_PT_REG 0x26
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#define Z8536_PB_PT_REG 0x2e
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#define Z8536_PA_PM_REG 0x27
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#define Z8536_PB_PM_REG 0x2f
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#endif /* _Z8536_H */
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