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soc: mediatek: pm-domains: Add support for mt8186

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Add power domain control data in mt8186.

Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220215104917.5726-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Chun-Jie Chen
2022-02-15 18:49:17 +08:00
committed by Matthias Brugger
parent c8a006896f
commit 88590cbc17
3 changed files with 397 additions and 0 deletions
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include/linux/soc/mediatek/infracfg.h
+48
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@@ -140,6 +140,54 @@
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
/* MFG1 */
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27))
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21))
#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25))
#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29))
/* DIS */
#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11))
#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10))
/* IMG */
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23))
#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15))
/* IPE */
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24))
#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16))
/* CAM */
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21))
#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13))
/* VENC */
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31))
#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19))
/* VDEC */
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30))
#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17))
/* WPE */
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17))
#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16))
/* CONN_ON */
#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18))
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14))
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13))
#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16))
/* ADSP_TOP */
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11))
#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
#define MT8183_TOP_AXI_PROT_EN_STA1 0x228
#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0