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drm/kmb: Add support for KeemBay Display
This is a basic KMS atomic modesetting display driver for KeemBay family of
SOCs. Driver has no 2D or 3D graphics. It calls into the ADV bridge
driver at the connector level.
Single CRTC with LCD controller->mipi DSI->ADV bridge
Only 1080p resolution and single plane is supported at this time.
v2: moved extern to .h, removed license text
use drm_dev_init, upclassed dev_private, removed HAVE_IRQ.(Sam)
v3: Squashed all 59 commits to one
v4: review changes from Sam Ravnborg
renamed dev_p to kmb
moved clocks under kmb_clock, consolidated clk initializations
use drmm functions
use DRM_GEM_CMA_DRIVER_OPS_VMAP
v5: corrected spellings
v6: corrected checkpatch warnings
v7: review changes Sam Ravnborg and Thomas Zimmerman
removed kmb_crtc.h kmb_crtc_cleanup (Thomas)
renamed mode_set, kmb_load, inlined unload (Thomas)
moved remaining logging to drm_*(Thomas)
re-orged driver initialization (Thomas)
moved plane_status to drm_private (Sam)
removed unnecessary logs and defines and ifdef codes (Sam)
call helper_check in plane_atomic_check (Sam)
renamed set to get for bpp and format functions(Sam)
use drm helper functions for reset, duplicate/destroy state instead
of kmb functions (Sam)
removed kmb_priv from kmb_plane and removed kmb_plane_state (Sam)
v8: get clk_pll0 from display node in dt
v9: moved csc_coef_lcd to plane.c (Daniel Vetter)
call drm_atomic_helper_shutdown in remove (Daniel V)
use drm_crtc_handle_vblank (Daniel V)
renamed kmb_dsi_hw_init to kmb_dsi_mode_set (Daniel V)
complimentary changes to device tree changes (Rob)
v10: call drm_crtc_arm_vblank_event in atomic_flush (Daniel V)
moved global vars to kmb_private and added locks (Daniel V)
changes in driver to accommodate changes in DT to separate DSI
entries (Sam R)
review changes to separate mipi DSI (Sam R)
v11: review changes to separate msscam (Neil A,Sam R)
v12: fixed warnings Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/1604538931-26726-6-git-send-email-anitha.chrisanthus@intel.com
This commit is contained in:
Anitha Chrisanthus
committed by
Sam Ravnborg
Sam Ravnborg
parent
1bb8b7fcda
commit
7f7b96a8a0
@@ -0,0 +1,214 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright © 2018-2020 Intel Corporation
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*/
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#include <linux/clk.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_print.h>
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#include <drm/drm_vblank.h>
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#include <drm/drm_modeset_helper_vtables.h>
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#include "kmb_drv.h"
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#include "kmb_dsi.h"
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#include "kmb_plane.h"
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#include "kmb_regs.h"
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struct kmb_crtc_timing {
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u32 vfront_porch;
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u32 vback_porch;
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u32 vsync_len;
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u32 hfront_porch;
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u32 hback_porch;
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u32 hsync_len;
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};
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static int kmb_crtc_enable_vblank(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct kmb_drm_private *kmb = to_kmb(dev);
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/* Clear interrupt */
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kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
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/* Set which interval to generate vertical interrupt */
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kmb_write_lcd(kmb, LCD_VSTATUS_COMPARE,
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LCD_VSTATUS_COMPARE_VSYNC);
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/* Enable vertical interrupt */
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kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE,
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LCD_INT_VERT_COMP);
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return 0;
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}
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static void kmb_crtc_disable_vblank(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct kmb_drm_private *kmb = to_kmb(dev);
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/* Clear interrupt */
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kmb_write_lcd(kmb, LCD_INT_CLEAR, LCD_INT_VERT_COMP);
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/* Disable vertical interrupt */
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kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
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LCD_INT_VERT_COMP);
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}
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static const struct drm_crtc_funcs kmb_crtc_funcs = {
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.destroy = drm_crtc_cleanup,
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.set_config = drm_atomic_helper_set_config,
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.page_flip = drm_atomic_helper_page_flip,
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.reset = drm_atomic_helper_crtc_reset,
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.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
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.enable_vblank = kmb_crtc_enable_vblank,
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.disable_vblank = kmb_crtc_disable_vblank,
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};
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static void kmb_crtc_set_mode(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_display_mode *m = &crtc->state->adjusted_mode;
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struct kmb_crtc_timing vm;
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struct kmb_drm_private *kmb = to_kmb(dev);
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unsigned int val = 0;
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/* Initialize mipi */
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kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz);
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drm_info(dev,
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"vfp= %d vbp= %d vsyc_len=%d hfp=%d hbp=%d hsync_len=%d\n",
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m->crtc_vsync_start - m->crtc_vdisplay,
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m->crtc_vtotal - m->crtc_vsync_end,
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m->crtc_vsync_end - m->crtc_vsync_start,
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m->crtc_hsync_start - m->crtc_hdisplay,
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m->crtc_htotal - m->crtc_hsync_end,
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m->crtc_hsync_end - m->crtc_hsync_start);
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val = kmb_read_lcd(kmb, LCD_INT_ENABLE);
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kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE, val);
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kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, ~0x0);
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vm.vfront_porch = 2;
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vm.vback_porch = 2;
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vm.vsync_len = 8;
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vm.hfront_porch = 0;
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vm.hback_porch = 0;
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vm.hsync_len = 28;
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drm_dbg(dev, "%s : %dactive height= %d vbp=%d vfp=%d vsync-w=%d h-active=%d h-bp=%d h-fp=%d hysnc-l=%d",
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__func__, __LINE__,
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m->crtc_vdisplay, vm.vback_porch, vm.vfront_porch,
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vm.vsync_len, m->crtc_hdisplay, vm.hback_porch,
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vm.hfront_porch, vm.hsync_len);
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kmb_write_lcd(kmb, LCD_V_ACTIVEHEIGHT,
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m->crtc_vdisplay - 1);
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kmb_write_lcd(kmb, LCD_V_BACKPORCH, vm.vback_porch);
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kmb_write_lcd(kmb, LCD_V_FRONTPORCH, vm.vfront_porch);
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kmb_write_lcd(kmb, LCD_VSYNC_WIDTH, vm.vsync_len - 1);
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kmb_write_lcd(kmb, LCD_H_ACTIVEWIDTH,
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m->crtc_hdisplay - 1);
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kmb_write_lcd(kmb, LCD_H_BACKPORCH, vm.hback_porch);
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kmb_write_lcd(kmb, LCD_H_FRONTPORCH, vm.hfront_porch);
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kmb_write_lcd(kmb, LCD_HSYNC_WIDTH, vm.hsync_len - 1);
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/* This is hardcoded as 0 in the Myriadx code */
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kmb_write_lcd(kmb, LCD_VSYNC_START, 0);
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kmb_write_lcd(kmb, LCD_VSYNC_END, 0);
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/* Back ground color */
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kmb_write_lcd(kmb, LCD_BG_COLOUR_LS, 0x4);
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if (m->flags == DRM_MODE_FLAG_INTERLACE) {
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kmb_write_lcd(kmb,
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LCD_VSYNC_WIDTH_EVEN, vm.vsync_len - 1);
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kmb_write_lcd(kmb,
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LCD_V_BACKPORCH_EVEN, vm.vback_porch);
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kmb_write_lcd(kmb,
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LCD_V_FRONTPORCH_EVEN, vm.vfront_porch);
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kmb_write_lcd(kmb, LCD_V_ACTIVEHEIGHT_EVEN,
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m->crtc_vdisplay - 1);
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/* This is hardcoded as 10 in the Myriadx code */
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kmb_write_lcd(kmb, LCD_VSYNC_START_EVEN, 10);
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kmb_write_lcd(kmb, LCD_VSYNC_END_EVEN, 10);
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}
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kmb_write_lcd(kmb, LCD_TIMING_GEN_TRIG, 1);
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kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_ENABLE);
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kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, val);
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}
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static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
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clk_prepare_enable(kmb->kmb_clk.clk_lcd);
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kmb_crtc_set_mode(crtc);
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drm_crtc_vblank_on(crtc);
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}
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static void kmb_crtc_atomic_disable(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
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struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
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/* due to hw limitations, planes need to be off when crtc is off */
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drm_atomic_helper_disable_planes_on_crtc(old_state, false);
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drm_crtc_vblank_off(crtc);
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clk_disable_unprepare(kmb->kmb_clk.clk_lcd);
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}
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static void kmb_crtc_atomic_begin(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct drm_device *dev = crtc->dev;
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struct kmb_drm_private *kmb = to_kmb(dev);
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kmb_clr_bitmask_lcd(kmb, LCD_INT_ENABLE,
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LCD_INT_VERT_COMP);
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}
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static void kmb_crtc_atomic_flush(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct drm_device *dev = crtc->dev;
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struct kmb_drm_private *kmb = to_kmb(dev);
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kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE,
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LCD_INT_VERT_COMP);
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spin_lock_irq(&crtc->dev->event_lock);
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if (crtc->state->event) {
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if (drm_crtc_vblank_get(crtc) == 0)
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drm_crtc_arm_vblank_event(crtc, crtc->state->event);
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else
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drm_crtc_send_vblank_event(crtc, crtc->state->event);
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}
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crtc->state->event = NULL;
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = {
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.atomic_begin = kmb_crtc_atomic_begin,
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.atomic_enable = kmb_crtc_atomic_enable,
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.atomic_disable = kmb_crtc_atomic_disable,
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.atomic_flush = kmb_crtc_atomic_flush,
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};
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int kmb_setup_crtc(struct drm_device *drm)
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{
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struct kmb_drm_private *kmb = to_kmb(drm);
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struct kmb_plane *primary;
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int ret;
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primary = kmb_plane_init(drm);
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if (IS_ERR(primary))
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return PTR_ERR(primary);
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ret = drm_crtc_init_with_planes(drm, &kmb->crtc, &primary->base_plane,
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NULL, &kmb_crtc_funcs, NULL);
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if (ret) {
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kmb_plane_destroy(&primary->base_plane);
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return ret;
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}
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drm_crtc_helper_add(&kmb->crtc, &kmb_crtc_helper_funcs);
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return 0;
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,88 @@
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/* SPDX-License-Identifier: GPL-2.0-only
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*
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* Copyright © 2018-2020 Intel Corporation
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*/
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#ifndef __KMB_DRV_H__
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#define __KMB_DRV_H__
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#include <drm/drm_device.h>
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#include "kmb_plane.h"
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#include "kmb_regs.h"
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#define KMB_MAX_WIDTH 1920 /*Max width in pixels */
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#define KMB_MAX_HEIGHT 1080 /*Max height in pixels */
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#define KMB_MIN_WIDTH 1920 /*Max width in pixels */
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#define KMB_MIN_HEIGHT 1080 /*Max height in pixels */
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#define KMB_LCD_DEFAULT_CLK 200000000
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#define KMB_SYS_CLK_MHZ 500
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#define ICAM_MMIO 0x3b100000
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#define ICAM_LCD_OFFSET 0x1080
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#define ICAM_MMIO_SIZE 0x2000
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struct kmb_dsi;
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struct kmb_clock {
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struct clk *clk_lcd;
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struct clk *clk_pll0;
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};
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struct kmb_drm_private {
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struct drm_device drm;
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struct kmb_dsi *kmb_dsi;
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void __iomem *lcd_mmio;
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struct kmb_clock kmb_clk;
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struct drm_crtc crtc;
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struct kmb_plane *plane;
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struct drm_atomic_state *state;
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spinlock_t irq_lock;
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int irq_lcd;
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int sys_clk_mhz;
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struct layer_status plane_status[KMB_MAX_PLANES];
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int kmb_under_flow;
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int kmb_flush_done;
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int layer_no;
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};
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static inline struct kmb_drm_private *to_kmb(const struct drm_device *dev)
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{
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return container_of(dev, struct kmb_drm_private, drm);
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}
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static inline struct kmb_drm_private *crtc_to_kmb_priv(const struct drm_crtc *x)
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{
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return container_of(x, struct kmb_drm_private, crtc);
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}
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static inline void kmb_write_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 value)
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{
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writel(value, (dev_p->lcd_mmio + reg));
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}
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static inline u32 kmb_read_lcd(struct kmb_drm_private *dev_p, unsigned int reg)
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{
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return readl(dev_p->lcd_mmio + reg);
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}
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static inline void kmb_set_bitmask_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 mask)
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{
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u32 reg_val = kmb_read_lcd(dev_p, reg);
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kmb_write_lcd(dev_p, reg, (reg_val | mask));
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}
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static inline void kmb_clr_bitmask_lcd(struct kmb_drm_private *dev_p,
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unsigned int reg, u32 mask)
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{
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u32 reg_val = kmb_read_lcd(dev_p, reg);
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kmb_write_lcd(dev_p, reg, (reg_val & (~mask)));
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}
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int kmb_setup_crtc(struct drm_device *dev);
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void kmb_set_scanout(struct kmb_drm_private *lcd);
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#endif /* __KMB_DRV_H__ */
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@@ -0,0 +1,490 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright © 2018-2020 Intel Corporation
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*/
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_fourcc.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_plane_helper.h>
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#include "kmb_drv.h"
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#include "kmb_plane.h"
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#include "kmb_regs.h"
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const u32 layer_irqs[] = {
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LCD_INT_VL0,
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LCD_INT_VL1,
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LCD_INT_GL0,
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LCD_INT_GL1
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};
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/* Conversion (yuv->rgb) matrix from myriadx */
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static const u32 csc_coef_lcd[] = {
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1024, 0, 1436,
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1024, -352, -731,
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1024, 1814, 0,
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-179, 125, -226
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};
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static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
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{
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int i;
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for (i = 0; i < plane->format_count; i++) {
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if (plane->format_types[i] == format)
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return 0;
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}
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return -EINVAL;
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}
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static int kmb_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_framebuffer *fb;
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int ret;
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struct drm_crtc_state *crtc_state;
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bool can_position;
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fb = state->fb;
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if (!fb || !state->crtc)
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return 0;
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ret = check_pixel_format(plane, fb->format->format);
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if (ret)
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return ret;
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if (state->crtc_w > KMB_MAX_WIDTH || state->crtc_h > KMB_MAX_HEIGHT)
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return -EINVAL;
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if (state->crtc_w < KMB_MIN_WIDTH || state->crtc_h < KMB_MIN_HEIGHT)
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return -EINVAL;
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can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
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crtc_state =
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drm_atomic_get_existing_crtc_state(state->state, state->crtc);
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return drm_atomic_helper_check_plane_state(state, crtc_state,
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DRM_PLANE_HELPER_NO_SCALING,
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DRM_PLANE_HELPER_NO_SCALING,
|
||||
can_position, true);
|
||||
}
|
||||
|
||||
static void kmb_plane_atomic_disable(struct drm_plane *plane,
|
||||
struct drm_plane_state *state)
|
||||
{
|
||||
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
|
||||
int plane_id = kmb_plane->id;
|
||||
struct kmb_drm_private *kmb;
|
||||
|
||||
kmb = to_kmb(plane->dev);
|
||||
|
||||
switch (plane_id) {
|
||||
case LAYER_0:
|
||||
kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE;
|
||||
break;
|
||||
case LAYER_1:
|
||||
kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE;
|
||||
break;
|
||||
case LAYER_2:
|
||||
kmb->plane_status[plane_id].ctrl = LCD_CTRL_GL1_ENABLE;
|
||||
break;
|
||||
case LAYER_3:
|
||||
kmb->plane_status[plane_id].ctrl = LCD_CTRL_GL2_ENABLE;
|
||||
break;
|
||||
}
|
||||
|
||||
kmb->plane_status[plane_id].disable = true;
|
||||
}
|
||||
|
||||
static unsigned int get_pixel_format(u32 format)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
switch (format) {
|
||||
/* planar formats */
|
||||
case DRM_FORMAT_YUV444:
|
||||
val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE;
|
||||
break;
|
||||
case DRM_FORMAT_YVU444:
|
||||
val = LCD_LAYER_FORMAT_YCBCR444PLAN | LCD_LAYER_PLANAR_STORAGE
|
||||
| LCD_LAYER_CRCB_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_YUV422:
|
||||
val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE;
|
||||
break;
|
||||
case DRM_FORMAT_YVU422:
|
||||
val = LCD_LAYER_FORMAT_YCBCR422PLAN | LCD_LAYER_PLANAR_STORAGE
|
||||
| LCD_LAYER_CRCB_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_YUV420:
|
||||
val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE;
|
||||
break;
|
||||
case DRM_FORMAT_YVU420:
|
||||
val = LCD_LAYER_FORMAT_YCBCR420PLAN | LCD_LAYER_PLANAR_STORAGE
|
||||
| LCD_LAYER_CRCB_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_NV12:
|
||||
val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE;
|
||||
break;
|
||||
case DRM_FORMAT_NV21:
|
||||
val = LCD_LAYER_FORMAT_NV12 | LCD_LAYER_PLANAR_STORAGE
|
||||
| LCD_LAYER_CRCB_ORDER;
|
||||
break;
|
||||
/* packed formats */
|
||||
/* looks hw requires B & G to be swapped when RGB */
|
||||
case DRM_FORMAT_RGB332:
|
||||
val = LCD_LAYER_FORMAT_RGB332 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_XBGR4444:
|
||||
val = LCD_LAYER_FORMAT_RGBX4444;
|
||||
break;
|
||||
case DRM_FORMAT_ARGB4444:
|
||||
val = LCD_LAYER_FORMAT_RGBA4444 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_ABGR4444:
|
||||
val = LCD_LAYER_FORMAT_RGBA4444;
|
||||
break;
|
||||
case DRM_FORMAT_XRGB1555:
|
||||
val = LCD_LAYER_FORMAT_XRGB1555 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_XBGR1555:
|
||||
val = LCD_LAYER_FORMAT_XRGB1555;
|
||||
break;
|
||||
case DRM_FORMAT_ARGB1555:
|
||||
val = LCD_LAYER_FORMAT_RGBA1555 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_ABGR1555:
|
||||
val = LCD_LAYER_FORMAT_RGBA1555;
|
||||
break;
|
||||
case DRM_FORMAT_RGB565:
|
||||
val = LCD_LAYER_FORMAT_RGB565 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_BGR565:
|
||||
val = LCD_LAYER_FORMAT_RGB565;
|
||||
break;
|
||||
case DRM_FORMAT_RGB888:
|
||||
val = LCD_LAYER_FORMAT_RGB888 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_BGR888:
|
||||
val = LCD_LAYER_FORMAT_RGB888;
|
||||
break;
|
||||
case DRM_FORMAT_XRGB8888:
|
||||
val = LCD_LAYER_FORMAT_RGBX8888 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_XBGR8888:
|
||||
val = LCD_LAYER_FORMAT_RGBX8888;
|
||||
break;
|
||||
case DRM_FORMAT_ARGB8888:
|
||||
val = LCD_LAYER_FORMAT_RGBA8888 | LCD_LAYER_BGR_ORDER;
|
||||
break;
|
||||
case DRM_FORMAT_ABGR8888:
|
||||
val = LCD_LAYER_FORMAT_RGBA8888;
|
||||
break;
|
||||
}
|
||||
DRM_INFO_ONCE("%s : %d format=0x%x val=0x%x\n",
|
||||
__func__, __LINE__, format, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
static unsigned int get_bits_per_pixel(const struct drm_format_info *format)
|
||||
{
|
||||
u32 bpp = 0;
|
||||
unsigned int val = 0;
|
||||
|
||||
if (format->num_planes > 1) {
|
||||
val = LCD_LAYER_8BPP;
|
||||
return val;
|
||||
}
|
||||
|
||||
bpp += 8 * format->cpp[0];
|
||||
|
||||
switch (bpp) {
|
||||
case 8:
|
||||
val = LCD_LAYER_8BPP;
|
||||
break;
|
||||
case 16:
|
||||
val = LCD_LAYER_16BPP;
|
||||
break;
|
||||
case 24:
|
||||
val = LCD_LAYER_24BPP;
|
||||
break;
|
||||
case 32:
|
||||
val = LCD_LAYER_32BPP;
|
||||
break;
|
||||
}
|
||||
|
||||
DRM_DEBUG("bpp=%d val=0x%x\n", bpp, val);
|
||||
return val;
|
||||
}
|
||||
|
||||
static void config_csc(struct kmb_drm_private *kmb, int plane_id)
|
||||
{
|
||||
/* YUV to RGB conversion using the fixed matrix csc_coef_lcd */
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]);
|
||||
}
|
||||
|
||||
static void kmb_plane_atomic_update(struct drm_plane *plane,
|
||||
struct drm_plane_state *state)
|
||||
{
|
||||
struct drm_framebuffer *fb;
|
||||
struct kmb_drm_private *kmb;
|
||||
unsigned int width;
|
||||
unsigned int height;
|
||||
unsigned int dma_len;
|
||||
struct kmb_plane *kmb_plane;
|
||||
unsigned int dma_cfg;
|
||||
unsigned int ctrl = 0, val = 0, out_format = 0;
|
||||
unsigned int src_w, src_h, crtc_x, crtc_y;
|
||||
unsigned char plane_id;
|
||||
int num_planes;
|
||||
static dma_addr_t addr[MAX_SUB_PLANES];
|
||||
|
||||
if (!plane || !plane->state || !state)
|
||||
return;
|
||||
|
||||
fb = plane->state->fb;
|
||||
if (!fb)
|
||||
return;
|
||||
num_planes = fb->format->num_planes;
|
||||
kmb_plane = to_kmb_plane(plane);
|
||||
plane_id = kmb_plane->id;
|
||||
|
||||
kmb = to_kmb(plane->dev);
|
||||
|
||||
spin_lock_irq(&kmb->irq_lock);
|
||||
if (kmb->kmb_under_flow || kmb->kmb_flush_done) {
|
||||
spin_unlock_irq(&kmb->irq_lock);
|
||||
drm_dbg(&kmb->drm, "plane_update:underflow!!!! returning");
|
||||
return;
|
||||
}
|
||||
spin_unlock_irq(&kmb->irq_lock);
|
||||
|
||||
src_w = (plane->state->src_w >> 16);
|
||||
src_h = plane->state->src_h >> 16;
|
||||
crtc_x = plane->state->crtc_x;
|
||||
crtc_y = plane->state->crtc_y;
|
||||
|
||||
drm_dbg(&kmb->drm,
|
||||
"src_w=%d src_h=%d, fb->format->format=0x%x fb->flags=0x%x\n",
|
||||
src_w, src_h, fb->format->format, fb->flags);
|
||||
|
||||
width = fb->width;
|
||||
height = fb->height;
|
||||
dma_len = (width * height * fb->format->cpp[0]);
|
||||
drm_dbg(&kmb->drm, "dma_len=%d ", dma_len);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id),
|
||||
fb->pitches[0]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id),
|
||||
(width * fb->format->cpp[0]));
|
||||
|
||||
addr[Y_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state, 0);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_START_ADDR(plane_id),
|
||||
addr[Y_PLANE] + fb->offsets[0]);
|
||||
val = get_pixel_format(fb->format->format);
|
||||
val |= get_bits_per_pixel(fb->format);
|
||||
/* Program Cb/Cr for planar formats */
|
||||
if (num_planes > 1) {
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id),
|
||||
width * fb->format->cpp[0]);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id),
|
||||
(width * fb->format->cpp[0]));
|
||||
|
||||
addr[U_PLANE] = drm_fb_cma_get_gem_addr(fb, plane->state,
|
||||
U_PLANE);
|
||||
/* check if Cb/Cr is swapped*/
|
||||
if (num_planes == 3 && (val & LCD_LAYER_CRCB_ORDER))
|
||||
kmb_write_lcd(kmb,
|
||||
LCD_LAYERn_DMA_START_CR_ADR(plane_id),
|
||||
addr[U_PLANE]);
|
||||
else
|
||||
kmb_write_lcd(kmb,
|
||||
LCD_LAYERn_DMA_START_CB_ADR(plane_id),
|
||||
addr[U_PLANE]);
|
||||
|
||||
if (num_planes == 3) {
|
||||
kmb_write_lcd(kmb,
|
||||
LCD_LAYERn_DMA_CR_LINE_VSTRIDE(plane_id),
|
||||
((width) * fb->format->cpp[0]));
|
||||
|
||||
kmb_write_lcd(kmb,
|
||||
LCD_LAYERn_DMA_CR_LINE_WIDTH(plane_id),
|
||||
((width) * fb->format->cpp[0]));
|
||||
|
||||
addr[V_PLANE] = drm_fb_cma_get_gem_addr(fb,
|
||||
plane->state,
|
||||
V_PLANE);
|
||||
|
||||
/* check if Cb/Cr is swapped*/
|
||||
if (val & LCD_LAYER_CRCB_ORDER)
|
||||
kmb_write_lcd(kmb,
|
||||
LCD_LAYERn_DMA_START_CB_ADR(plane_id),
|
||||
addr[V_PLANE]);
|
||||
else
|
||||
kmb_write_lcd(kmb,
|
||||
LCD_LAYERn_DMA_START_CR_ADR(plane_id),
|
||||
addr[V_PLANE]);
|
||||
}
|
||||
}
|
||||
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_WIDTH(plane_id), src_w - 1);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_HEIGHT(plane_id), src_h - 1);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_COL_START(plane_id), crtc_x);
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_ROW_START(plane_id), crtc_y);
|
||||
|
||||
val |= LCD_LAYER_FIFO_100;
|
||||
|
||||
if (val & LCD_LAYER_PLANAR_STORAGE) {
|
||||
val |= LCD_LAYER_CSC_EN;
|
||||
|
||||
/* Enable CSC if input is planar and output is RGB */
|
||||
config_csc(kmb, plane_id);
|
||||
}
|
||||
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_CFG(plane_id), val);
|
||||
|
||||
switch (plane_id) {
|
||||
case LAYER_0:
|
||||
ctrl = LCD_CTRL_VL1_ENABLE;
|
||||
break;
|
||||
case LAYER_1:
|
||||
ctrl = LCD_CTRL_VL2_ENABLE;
|
||||
break;
|
||||
case LAYER_2:
|
||||
ctrl = LCD_CTRL_GL1_ENABLE;
|
||||
break;
|
||||
case LAYER_3:
|
||||
ctrl = LCD_CTRL_GL2_ENABLE;
|
||||
break;
|
||||
}
|
||||
|
||||
ctrl |= LCD_CTRL_PROGRESSIVE | LCD_CTRL_TIM_GEN_ENABLE
|
||||
| LCD_CTRL_CONTINUOUS | LCD_CTRL_OUTPUT_ENABLED;
|
||||
|
||||
/* LCD is connected to MIPI on kmb
|
||||
* Therefore this bit is required for DSI Tx
|
||||
*/
|
||||
ctrl |= LCD_CTRL_VHSYNC_IDLE_LVL;
|
||||
|
||||
kmb_set_bitmask_lcd(kmb, LCD_CONTROL, ctrl);
|
||||
|
||||
/* FIXME no doc on how to set output format,these values are
|
||||
* taken from the Myriadx tests
|
||||
*/
|
||||
out_format |= LCD_OUTF_FORMAT_RGB888;
|
||||
|
||||
/* Leave RGB order,conversion mode and clip mode to default */
|
||||
/* do not interleave RGB channels for mipi Tx compatibility */
|
||||
out_format |= LCD_OUTF_MIPI_RGB_MODE;
|
||||
kmb_write_lcd(kmb, LCD_OUT_FORMAT_CFG, out_format);
|
||||
|
||||
dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN |
|
||||
LCD_DMA_LAYER_CONT_UPDATE | LCD_DMA_LAYER_AXI_BURST_16;
|
||||
|
||||
/* Enable DMA */
|
||||
kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
|
||||
drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg,
|
||||
kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id)));
|
||||
|
||||
kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF |
|
||||
LCD_INT_DMA_ERR);
|
||||
kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, LCD_INT_EOF |
|
||||
LCD_INT_DMA_ERR);
|
||||
}
|
||||
|
||||
static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = {
|
||||
.atomic_check = kmb_plane_atomic_check,
|
||||
.atomic_update = kmb_plane_atomic_update,
|
||||
.atomic_disable = kmb_plane_atomic_disable
|
||||
};
|
||||
|
||||
void kmb_plane_destroy(struct drm_plane *plane)
|
||||
{
|
||||
struct kmb_plane *kmb_plane = to_kmb_plane(plane);
|
||||
|
||||
drm_plane_cleanup(plane);
|
||||
kfree(kmb_plane);
|
||||
}
|
||||
|
||||
static const struct drm_plane_funcs kmb_plane_funcs = {
|
||||
.update_plane = drm_atomic_helper_update_plane,
|
||||
.disable_plane = drm_atomic_helper_disable_plane,
|
||||
.destroy = kmb_plane_destroy,
|
||||
.reset = drm_atomic_helper_plane_reset,
|
||||
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
|
||||
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
||||
};
|
||||
|
||||
struct kmb_plane *kmb_plane_init(struct drm_device *drm)
|
||||
{
|
||||
struct kmb_drm_private *kmb = to_kmb(drm);
|
||||
struct kmb_plane *plane = NULL;
|
||||
struct kmb_plane *primary = NULL;
|
||||
int i = 0;
|
||||
int ret = 0;
|
||||
enum drm_plane_type plane_type;
|
||||
const u32 *plane_formats;
|
||||
int num_plane_formats;
|
||||
|
||||
for (i = 0; i < KMB_MAX_PLANES; i++) {
|
||||
plane = drmm_kzalloc(drm, sizeof(*plane), GFP_KERNEL);
|
||||
|
||||
if (!plane) {
|
||||
drm_err(drm, "Failed to allocate plane\n");
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
|
||||
DRM_PLANE_TYPE_OVERLAY;
|
||||
if (i < 2) {
|
||||
plane_formats = kmb_formats_v;
|
||||
num_plane_formats = ARRAY_SIZE(kmb_formats_v);
|
||||
} else {
|
||||
plane_formats = kmb_formats_g;
|
||||
num_plane_formats = ARRAY_SIZE(kmb_formats_g);
|
||||
}
|
||||
|
||||
ret = drm_universal_plane_init(drm, &plane->base_plane,
|
||||
POSSIBLE_CRTCS, &kmb_plane_funcs,
|
||||
plane_formats, num_plane_formats,
|
||||
NULL, plane_type, "plane %d", i);
|
||||
if (ret < 0) {
|
||||
drm_err(drm, "drm_universal_plane_init failed (ret=%d)",
|
||||
ret);
|
||||
goto cleanup;
|
||||
}
|
||||
drm_dbg(drm, "%s : %d i=%d type=%d",
|
||||
__func__, __LINE__,
|
||||
i, plane_type);
|
||||
drm_plane_helper_add(&plane->base_plane,
|
||||
&kmb_plane_helper_funcs);
|
||||
if (plane_type == DRM_PLANE_TYPE_PRIMARY) {
|
||||
primary = plane;
|
||||
kmb->plane = plane;
|
||||
}
|
||||
drm_dbg(drm, "%s : %d primary=%p\n", __func__, __LINE__,
|
||||
&primary->base_plane);
|
||||
plane->id = i;
|
||||
}
|
||||
|
||||
return primary;
|
||||
cleanup:
|
||||
drmm_kfree(drm, plane);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
@@ -0,0 +1,99 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only
|
||||
*
|
||||
* Copyright © 2018-2020 Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __KMB_PLANE_H__
|
||||
#define __KMB_PLANE_H__
|
||||
|
||||
#include <drm/drm_fourcc.h>
|
||||
#include <drm/drm_plane.h>
|
||||
|
||||
#define LCD_INT_VL0_ERR ((LAYER0_DMA_FIFO_UNDERFLOW) | \
|
||||
(LAYER0_DMA_FIFO_OVERFLOW) | \
|
||||
(LAYER0_DMA_CB_FIFO_OVERFLOW) | \
|
||||
(LAYER0_DMA_CB_FIFO_UNDERFLOW) | \
|
||||
(LAYER0_DMA_CR_FIFO_OVERFLOW) | \
|
||||
(LAYER0_DMA_CR_FIFO_UNDERFLOW))
|
||||
|
||||
#define LCD_INT_VL1_ERR ((LAYER1_DMA_FIFO_UNDERFLOW) | \
|
||||
(LAYER1_DMA_FIFO_OVERFLOW) | \
|
||||
(LAYER1_DMA_CB_FIFO_OVERFLOW) | \
|
||||
(LAYER1_DMA_CB_FIFO_UNDERFLOW) | \
|
||||
(LAYER1_DMA_CR_FIFO_OVERFLOW) | \
|
||||
(LAYER1_DMA_CR_FIFO_UNDERFLOW))
|
||||
|
||||
#define LCD_INT_GL0_ERR (LAYER2_DMA_FIFO_OVERFLOW | LAYER2_DMA_FIFO_UNDERFLOW)
|
||||
#define LCD_INT_GL1_ERR (LAYER3_DMA_FIFO_OVERFLOW | LAYER3_DMA_FIFO_UNDERFLOW)
|
||||
#define LCD_INT_VL0 (LAYER0_DMA_DONE | LAYER0_DMA_IDLE | LCD_INT_VL0_ERR)
|
||||
#define LCD_INT_VL1 (LAYER1_DMA_DONE | LAYER1_DMA_IDLE | LCD_INT_VL1_ERR)
|
||||
#define LCD_INT_GL0 (LAYER2_DMA_DONE | LAYER2_DMA_IDLE | LCD_INT_GL0_ERR)
|
||||
#define LCD_INT_GL1 (LAYER3_DMA_DONE | LAYER3_DMA_IDLE | LCD_INT_GL1_ERR)
|
||||
#define LCD_INT_DMA_ERR (LCD_INT_VL0_ERR | LCD_INT_VL1_ERR \
|
||||
| LCD_INT_GL0_ERR | LCD_INT_GL1_ERR)
|
||||
|
||||
#define POSSIBLE_CRTCS 1
|
||||
#define to_kmb_plane(x) container_of(x, struct kmb_plane, base_plane)
|
||||
|
||||
enum layer_id {
|
||||
LAYER_0,
|
||||
LAYER_1,
|
||||
LAYER_2,
|
||||
LAYER_3,
|
||||
/* KMB_MAX_PLANES */
|
||||
};
|
||||
|
||||
#define KMB_MAX_PLANES 1
|
||||
|
||||
enum sub_plane_id {
|
||||
Y_PLANE,
|
||||
U_PLANE,
|
||||
V_PLANE,
|
||||
MAX_SUB_PLANES,
|
||||
};
|
||||
|
||||
struct kmb_plane {
|
||||
struct drm_plane base_plane;
|
||||
unsigned char id;
|
||||
};
|
||||
|
||||
/* Graphics layer (layers 2 & 3) formats, only packed formats are supported */
|
||||
static const u32 kmb_formats_g[] = {
|
||||
DRM_FORMAT_RGB332,
|
||||
DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444,
|
||||
DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444,
|
||||
DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555,
|
||||
DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555,
|
||||
DRM_FORMAT_RGB565, DRM_FORMAT_BGR565,
|
||||
DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
|
||||
DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888,
|
||||
};
|
||||
|
||||
/* Video layer ( 0 & 1) formats, packed and planar formats are supported */
|
||||
static const u32 kmb_formats_v[] = {
|
||||
/* packed formats */
|
||||
DRM_FORMAT_RGB332,
|
||||
DRM_FORMAT_XRGB4444, DRM_FORMAT_XBGR4444,
|
||||
DRM_FORMAT_ARGB4444, DRM_FORMAT_ABGR4444,
|
||||
DRM_FORMAT_XRGB1555, DRM_FORMAT_XBGR1555,
|
||||
DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR1555,
|
||||
DRM_FORMAT_RGB565, DRM_FORMAT_BGR565,
|
||||
DRM_FORMAT_RGB888, DRM_FORMAT_BGR888,
|
||||
DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888,
|
||||
DRM_FORMAT_ARGB8888, DRM_FORMAT_ABGR8888,
|
||||
/*planar formats */
|
||||
DRM_FORMAT_YUV420, DRM_FORMAT_YVU420,
|
||||
DRM_FORMAT_YUV422, DRM_FORMAT_YVU422,
|
||||
DRM_FORMAT_YUV444, DRM_FORMAT_YVU444,
|
||||
DRM_FORMAT_NV12, DRM_FORMAT_NV21,
|
||||
};
|
||||
|
||||
struct layer_status {
|
||||
bool disable;
|
||||
u32 ctrl;
|
||||
};
|
||||
|
||||
struct kmb_plane *kmb_plane_init(struct drm_device *drm);
|
||||
void kmb_plane_destroy(struct drm_plane *plane);
|
||||
#endif /* __KMB_PLANE_H__ */
|
||||
Reference in New Issue
Block a user