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dt-bindings: Improve phandle-array schemas

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The 'phandle-array' type is a bit ambiguous. It can be either just an
array of phandles or an array of phandles plus args. Many schemas for
phandle-array properties aren't clear in the schema which case applies
though the description usually describes it.

The array of phandles case boils down to needing:

items:
  maxItems: 1

The phandle plus args cases should typically take this form:

items:
  - items:
      - description: A phandle
      - description: 1st arg cell
      - description: 2nd arg cell

With this change, some examples need updating so that the bracketing of
property values matches the schema.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Georgi Djakov <djakov@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20220119015038.2433585-1-robh@kernel.org
This commit is contained in:
Rob Herring
2022-01-18 19:50:38 -06:00
parent 5a04982df8
commit 39bd2b6a37
67 changed files with 318 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@@ -243,6 +243,8 @@ properties:
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
items:
maxItems: 1
description: |
List of phandles to idle state nodes supported
by this cpu (see ./idle-states.yaml).

80
Documentation/devicetree/bindings/arm/idle-states.yaml
View File

@@ -337,8 +337,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@1 {
@@ -346,8 +346,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100 {
@@ -355,8 +355,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@101 {
@@ -364,8 +364,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10000 {
@@ -373,8 +373,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10000>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10001 {
@@ -382,8 +382,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10001>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10100 {
@@ -391,8 +391,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10101 {
@@ -400,8 +400,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100000000 {
@@ -409,8 +409,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000001 {
@@ -418,8 +418,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000100 {
@@ -427,8 +427,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000101 {
@@ -436,8 +436,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010000 {
@@ -445,8 +445,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10000>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010001 {
@@ -454,8 +454,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10001>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010100 {
@@ -463,8 +463,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010101 {
@@ -472,8 +472,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
idle-states {
@@ -567,56 +567,56 @@ examples:
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
idle-states {

2
Documentation/devicetree/bindings/arm/pmu.yaml
View File

@@ -66,6 +66,8 @@ properties:
interrupt-affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
When using SPIs, specifies a list of phandles to CPU
nodes corresponding directly to the affinity of

3
Documentation/devicetree/bindings/ata/sata_highbank.yaml
View File

@@ -51,6 +51,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
items:
minItems: 2
maxItems: 2
calxeda,tx-atten:
description: |

5
Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
View File

@@ -35,7 +35,10 @@ properties:
The SRAM that needs to be claimed to access the display engine
bus.
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
items:
- items:
- description: phandle to SRAM
- description: register value for device
ranges: true

15
Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
View File

@@ -22,19 +22,28 @@ properties:
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
items:
- items:
- description: phandle to the NPE this crypto engine
- description: the NPE instance number
description: phandle to the NPE this crypto engine is using, the cell
describing the NPE instance to be used.
queue-rx:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
items:
- items:
- description: phandle to the RX queue on the NPE
- description: the queue instance number
description: phandle to the RX queue on the NPE, the cell describing
the queue instance to be used.
queue-txready:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
items:
- items:
- description: phandle to the TX READY queue on the NPE
- description: the queue instance number
description: phandle to the TX READY queue on the NPE, the cell describing
the queue instance to be used.

2
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
View File

@@ -69,6 +69,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
items:
maxItems: 1
description: |
Available display engine frontends (DE 1.0) or mixers (DE
2.0/3.0) available.

5
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
View File

@@ -51,7 +51,10 @@ properties:
mediatek,syscon-hdmi:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
items:
- items:
- description: phandle to system configuration registers
- description: register offset in the system configuration registers
description: |
phandle link and register offset to the system configuration registers.

2
Documentation/devicetree/bindings/display/msm/gpu.yaml
View File

@@ -64,6 +64,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
items:
maxItems: 1
description: |
phandles to one or more reserved on-chip SRAM regions.
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and

10
Documentation/devicetree/bindings/display/renesas,du.yaml
View File

@@ -76,17 +76,21 @@ properties:
renesas,cmms:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
maxItems: 1
description:
A list of phandles to the CMM instances present in the SoC, one for each
available DU channel.
renesas,vsps:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
items:
- description: phandle to VSP instance that serves the DU channel
- description: Channel index identifying the LIF instance in that VSP
description:
A list of phandle and channel index tuples to the VSPs that handle the
memory interfaces for the DU channels. The phandle identifies the VSP
instance that serves the DU channel, and the channel index identifies
the LIF instance in that VSP.
memory interfaces for the DU channels.
required:
- compatible

2
Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
View File

@@ -21,6 +21,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
Should contain a list of phandles pointing to display interface port
of vop devices. vop definitions as defined in

2
Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml
View File

@@ -45,6 +45,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Should contain a list of phandles pointing to display interface port
of DPU devices.

3
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
View File

@@ -88,8 +88,7 @@ properties:
The DSS DPI output port node from video port 2
ti,am65x-oldi-io-ctrl:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
maxItems: 1
$ref: "/schemas/types.yaml#/definitions/phandle"
description:
phandle to syscon device node mapping OLDI IO_CTRL registers.
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and

2
Documentation/devicetree/bindings/dma/dma-router.yaml
View File

@@ -24,6 +24,8 @@ properties:
dma-masters:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Array of phandles to the DMA controllers the router can direct
the signal to.

2
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
View File

@@ -46,7 +46,7 @@ examples:
#dma-cells = <3>;
dma-requests = <128>;
dma-channels = <16>;
dma-masters = <&dma1 &dma2>;
dma-masters = <&dma1>, <&dma2>;
clocks = <&timer_clk>;
};

1
Documentation/devicetree/bindings/dvfs/performance-domain.yaml
View File

@@ -43,7 +43,6 @@ properties:
performance-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
description:
A phandle and performance domain specifier as defined by bindings of the
performance controller/provider specified by phandle.

2
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
View File

@@ -330,7 +330,7 @@ examples:
firmware {
scmi {
compatible = "arm,scmi-smc";
shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
arm,smc-id = <0xc3000001>;
#address-cells = <1>;

2
Documentation/devicetree/bindings/firmware/arm,scpi.yaml
View File

@@ -236,7 +236,7 @@ examples:
scpi {
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
shmem = <&cpu_scp_lpri>, <&cpu_scp_hpri>;
scpi_sensors1: sensors {
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";

2
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View File

@@ -121,6 +121,8 @@ properties:
qcom,bcm-voters:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
List of phandles to qcom,bcm-voter nodes that are required by
this interconnect to send RPMh commands.

6
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
View File

@@ -138,6 +138,8 @@ properties:
properties:
affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Should be a list of phandles to CPU nodes (as described in
Documentation/devicetree/bindings/arm/cpus.yaml).
@@ -273,11 +275,11 @@ examples:
ppi-partitions {
part0: interrupt-partition-0 {
affinity = <&cpu0 &cpu2>;
affinity = <&cpu0>, <&cpu2>;
};
part1: interrupt-partition-1 {
affinity = <&cpu1 &cpu3>;
affinity = <&cpu1>, <&cpu3>;
};
};
};

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