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Author SHA1 Message Date
Greg Kroah-Hartman 8e94114a40 Merge tag 'phy-fixes2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next 
Vinod writes:

phy: second round of phy fixes for v5.11

 - rockchip: init return and vednor prefix to dt-property
 - cpcap: bool conversion fix
 - lantiq: clock enable fix
 - lgm: kconfig depends on x86
 - mediatek: add mising MODULE_DEVICE_TABLE()

* tag 'phy-fixes2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: mediatek: Add missing MODULE_DEVICE_TABLE()
  phy: phy-brcm-sata: remove unneeded semicolon
  phy: USB_LGM_PHY should depend on X86
  phy: lantiq: rcu-usb2: wait after clock enable
  phy: rockchip: emmc, add vendor prefix to dts properties
  devicetree: phy: rockchip-emmc optional add vendor prefix
  phy: cpcap-usb: remove unneeded conversion to bool
  phy: rockchip-emmc: emmc_phy_init() always return 0
 2021-02-10 10:39:23 +01:00
Greg Kroah-Hartman 47ddb856c2 Merge tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next 
Vinod writes:

phy-for-5.12

 - Updates:
   - Conversion to YAML binding for:
        - mtk-xsphy
        - mtk-tphy
        - mtk-ufs
	- HDMI PHY
	- MIPI DSI PHY
	- brcmstb-usb-phy
   - Support for BCM4908 usb phy
   - Support for Qualcomm SDX55 USB and QMP phy
   - Support for Qualcomm SM8350 aka Snapdragon 888 UFS and USB phy
   - Support for Qualcomm SDM660 USB and UFS phy
   - Support for Qualcomm SC8180X USB and UFS phy
   - Support for Qualcomm IPQ6018 USB phy
   - Stm32 phy updates

* tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
  phy: cpcap-usb: Simplify bool conversion
  phy: qcom-qmp: make a const array static, makes object smaller
  phy: zynqmp: Simplify code by using dev_err_probe()
  phy: qcom-qmp: Add support for SM8350 UFS phy
  phy: qcom-qmp: Add UFS V5 registers found in SM8350
  dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings
  phy: qualcomm: usb28nm: Add MDM9607 init sequence
  dt-bindings: phy: qcom,qusb2: document ipq6018 compatible
  phy: qcom-qusb2: add QUSB2 support for IPQ6018
  phy: qcom-qmp: Add SC8180X USB phy
  phy: qcom-qmp: Add SC8180X UFS phy
  dt-bindings: phy: qcom,qmp: Add SC8180X USB phy
  dt-bindings: phy: qcom,qmp: Add SC8180X UFS to the QMP binding
  dt-bindings: phy: qcom-qusb2: Document SDM660 compatible
  phy: qcom-qusb2: Add configuration for SDM660
  phy: qcom-qusb2: Allow specifying default clock scheme
  dt-bindings: phy: qcom,usb-snps-femto-v2: Add SM8250 and SM8350 bindings
  phy: qcom-qmp: Add SM8350 USB QMP PHYs
  dt-bindings: phy: qcom,qmp: Add SM8150, SM8250 and SM8350 USB PHY bindings
  phy: qcom-qmp: Add support for SDX55 QMP PHY
  ...
 2021-02-09 09:32:35 +01:00
Yang Li d68f2cb095 phy: cpcap-usb: Simplify bool conversion 
Fix the following coccicheck warning:
./drivers/phy/motorola/phy-cpcap-usb.c:146:31-36: WARNING: conversion to
bool not needed here

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1611905915-50394-1-git-send-email-yang.lee@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-06 15:38:22 +05:30
Colin Ian King 43851904cb phy: qcom-qmp: make a const array static, makes object smaller 
Don't populate the const array cfg1_settings on the stack but instead make
it static. Makes the object code smaller by 24 bytes:

Before:
   text	   data	    bss	    dec	    hex	filename
  73585	  20240	     64	  93889	  16ec1	drivers/phy/qualcomm/phy-qcom-qmp.o

After:
   text	   data	    bss	    dec	    hex	filename
  73465	  20336	     64	  93865	  16ea9	drivers/phy/qualcomm/phy-qcom-qmp.o

(gcc version 10.2.0)

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210204180313.108876-1-colin.king@canonical.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-06 15:33:22 +05:30
Michal Simek 3dbbc8e97c phy: zynqmp: Simplify code by using dev_err_probe() 
Use already prepared dev_err_probe() introduced by commit a787e5400a
("driver core: add device probe log helper").
It simplifies EPROBE_DEFER handling.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/0df30548f721b10475a6cc5659beda102fec3c87.1612444300.git.michal.simek@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-06 15:28:15 +05:30
Vinod Koul 0e43fdb94a phy: qcom-qmp: Add support for SM8350 UFS phy 
Add the tables for init sequences for UFS QMP phy found in  SM8350 SoC.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-06 15:24:58 +05:30
Vinod Koul 920abc105b phy: qcom-qmp: Add UFS V5 registers found in SM8350 
Add the registers for UFS found in SM8350. The UFS phy used in SM8350
seems to have same offsets as V5 phy, although Documentation for that is
lacking.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-06 15:23:46 +05:30
Boris Brezillon 9a8b9434c6 phy: mediatek: Add missing MODULE_DEVICE_TABLE() 
This patch adds the missing MODULE_DEVICE_TABLE definitions on different
Mediatek phy drivers which generates correct modalias for automatic loading
when these drivers are compiled as an external module.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20210203110631.686003-1-enric.balletbo@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 13:37:37 +05:30
Yang Li 25e3ee590f phy: phy-brcm-sata: remove unneeded semicolon 
Eliminate the following coccicheck warning:
./drivers/phy/broadcom/phy-brcm-sata.c:654:2-3: Unneeded semicolon

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/1612321087-14743-1-git-send-email-yang.lee@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 13:37:26 +05:30
Konrad Dybcio 557a28811c phy: qualcomm: usb28nm: Add MDM9607 init sequence 
This is required to bring up the PHY on MDM9607-based boards.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 13:35:39 +05:30
Geert Uytterhoeven 6b46e60a69 phy: USB_LGM_PHY should depend on X86 
The Intel Lightning Mountain (LGM) USB3 USB is only present on Intel
Lightning Mountain SoCs.  Hence add a dependency on X86, to prevent
asking the user about this driver when configuring a kernel without
Intel Lightning Mountain platform support.

Fixes: 1cce8f73a5 ("phy: Add USB3 PHY support for Intel LGM SoC")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20210129131753.2656306-1-geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 13:32:53 +05:30
Kathiravan T 2cfbe6765b phy: qcom-qusb2: add QUSB2 support for IPQ6018 
Add the phy init sequence for the Super Speed ports found
on IPQ6018.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
[baruch: add ipq6018_regs_layout[], drop binding change]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 13:20:13 +05:30
Bjorn Andersson 4d1a6404e9 phy: qcom-qmp: Add SC8180X USB phy 
The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are
either the same or very similar to the same found in SM8150. Add a
compatible for this, reusing the existing SM8150 USB phy config.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210121014339.1612525-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 12:36:11 +05:30
Bjorn Andersson a5a621ad0a phy: qcom-qmp: Add SC8180X UFS phy 
The UFS phy found in the Qualcomm SC8180X is either the same or very
similar to the phy present in SM8150, so add a compatible and reuse the
SM8150 configuration.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210120224531.1610709-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-02-04 12:36:11 +05:30
AngeloGioacchino Del Regno b0e7f781fc phy: qcom-qusb2: Add configuration for SDM660 
The SDM660 SoC uses the same configuration as MSM8996, but the
clock scheme uses a differential reference clock and none of
the SoCs in this series (630, 636 and others) have got a usable
PHY_CLK_SCHEME register in the TCSR for clk scheme detection.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-19 20:37:54 +05:30
AngeloGioacchino Del Regno 26e6d50e93 phy: qcom-qusb2: Allow specifying default clock scheme 
The TCSR's PHY_CLK_SCHEME register is not available on all SoC
models, but some may still use a differential reference clock.

In preparation for these SoCs, add a se_clk_scheme_default
configuration entry and declare it to true for all currently
supported SoCs (retaining the previous defaults.

This patch brings no functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-19 20:36:01 +05:30
Jack Pham 10c744d48d phy: qcom-qmp: Add SM8350 USB QMP PHYs 
Add support for the USB DP & UNI PHYs found on SM8350. These use
version 5.0.0 of the QMP PHY IP and thus require new "V5"
definitions of the register offset macros for the QSERDES RX
and TX blocks. The QSERDES common and QPHY PCS blocks' register
offsets are largely unchanged from V4 so some of the existing
macros can be reused.

Signed-off-by: Jack Pham <jackp@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-19 20:32:31 +05:30
Manivannan Sadhasivam 86ef5a79d6 phy: qcom-qmp: Add support for SDX55 QMP PHY 
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses
version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210111113010.32056-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-17 12:24:56 +05:30
Amelie Delaunay 5b1af71280 phy: stm32: rework PLL Lock detection 
USBPHYC has a register per phy to control and monitor the debug interface
of the HS PHY through a digital debug access.
With this register, it is possible to know if PLL Lock input to phy is
high. That means the PLL is ready for HS operation.
Instead of using an hard-coded delay after PLL enable and PLL disable, use
this bit to ensure good operating of the HS PHY.
Also use an atomic counter (n_pll_cons) to count the actual number of PLL
consumers and get rid of stm32_usbphyc_has_one_phy_active.
The boolean active in the usbphyc_phy structure is kept, because we need to
know in remove if a phy_exit is required to properly disable the PLL.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-7-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 20:40:21 +05:30
Amelie Delaunay 649627245c phy: stm32: ensure phy are no more active when removing the driver 
To ensure a good balancing of regulators, and allow PLL disabling when the
driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys
inactive and disable PLL.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-6-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 20:40:21 +05:30
Amelie Delaunay 56bf858edd phy: stm32: ensure pll is disabled before phys creation 
To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-5-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 20:40:21 +05:30
Amelie Delaunay 04edf6d6e2 phy: stm32: replace regulator_bulk* by multiple regulator_* 
Due to async_schedule_domain call in regulator_bulk_enable,
scheduling while atomic bug can raise if regulator_bulk_enable is called
under atomic context.
To avoid this issue, this patch replaces all regulator_bulk* by regulator_
per regulators.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-4-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 20:40:21 +05:30
Amelie Delaunay 613a475f0b phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation 
PLL block requires to be powered with 1v1 and 1v8 supplies to catch
ENABLE signal.
Currently, supplies are managed through phy_ops .power_on/off, and PLL
activation/deactivation is managed through phy_ops .init/exit.
The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB
drivers dependent.
To ensure a good behavior of the PLL, supplies have to be managed at PLL
activation/deactivation. That means the supplies need to be put in usbphyc
node and not in phy children nodes.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20210105090525.23164-3-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 20:40:21 +05:30
Rafał Miłecki 4b402fa8e0 phy: phy-brcm-usb: support PHY on the BCM4908 
BCM4908 seems to have slightly different registers but works when
programmed just like the STB one.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Link: https://lore.kernel.org/r/20210106205838.10964-3-zajec5@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 19:45:40 +05:30
Zou Wei 6d54623a56 phy: mediatek: Mark mtk_mipi_tx_driver with static keyword 
Fix the following sparse warning:

drivers/phy/mediatek/phy-mtk-mipi-dsi.c:237:24: warning: symbol 'mtk_mipi_tx_driver' was not declared. Should it be static?

Signed-off-by: Zou Wei <zou_wei@huawei.com>
Link: https://lore.kernel.org/r/1610415484-92497-1-git-send-email-zou_wei@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2021-01-13 19:44:07 +05:30