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Merge branches 'at91', 'ep93xx', 'iop', 'kprobes', 'ks8695', 'misc', 'msm', 's3c2410', 'sa1100' and 'vfp' into devel
* at91: (24 commits) [ARM] 4615/4: sam926[13]ek buttons updated [ARM] 4765/1: [AT91] AT91CAP9A-DK board support [ARM] 4764/1: [AT91] AT91CAP9 core support [ARM] 4738/1: at91sam9261: Remove udc pullup enabling in board initialisation [ARM] 4761/1: [AT91] Board-support for NEW_LEDs [ARM] 4760/1: [AT91] SPI CS0 errata on AT91RM9200 [ARM] 4759/1: [AT91] Buttons on CSB300 [ARM] 4758/1: [AT91] LEDs [ARM] 4757/1: [AT91] UART initialization [ARM] 4756/1: [AT91] Makefile cleanup [ARM] 4755/1: [AT91] NAND update [ARM] 4754/1: [AT91] SSC library support [ARM] 4753/1: [AT91] Use DMA_BIT_MASK [ARM] 4752/1: [AT91] RTT, RTC and WDT peripherals on SAM9 [ARM] 4751/1: [AT91] ISI peripheral on SAM9263 [ARM] 4750/1: [AT91] STN LCD displays on SAM9261 [ARM] 4734/1: at91sam9263ek: include IRQ for Ethernet PHY [ARM] 4646/1: AT91: configurable HZ, default to 128 [ARM] 4688/1: at91: speed-up irq processing [ARM] 4657/1: AT91: Header definition update ... * ep93xx: [ARM] 4671/1: ep93xx: remove obsolete gpio_line_* operations [ARM] 4670/1: ep93xx: implement IRQT_BOTHEDGE gpio irq sense type [ARM] 4669/1: ep93xx: simplify GPIO code and cleanups [ARM] 4668/1: ep93xx: implement new GPIO API * iop: [ARM] 4770/1: GLAN Tank: correct physmap_flash_data width field [ARM] 4732/1: GLAN Tank: register rtc-rs5c372 i2c device [ARM] 4708/1: iop: update defconfigs for 2.6.24 * kprobes: ARM kprobes: let's enable it ARM kprobes: special hook for the kprobes breakpoint handler ARM kprobes: prevent some functions involved with kprobes from being probed ARM kprobes: don't let a single-stepped stmdb corrupt the exception stack ARM kprobes: add the kprobes hook to the page fault handler ARM kprobes: core code ARM kprobes: instruction single-stepping support * ks8695: [ARM] 4603/1: KS8695: debugfs interface to view pin state [ARM] 4601/1: KS8695: PCI support * misc: [ARM] remove duplicate includes [ARM] CONFIG_DEBUG_STACK_USAGE [ARM] 4689/1: small comment wrap fix [ARM] 4687/1: Trivial arch/arm/kernel/entry-common.S comment fix [ARM] 4666/1: ixp4xx: fix sparse warnings in include/asm-arm/arch-ixp4xx/io.h [ARM] remove reference to non-existent MTD_OBSOLETE_CHIPS [SERIAL] 21285: Report baud rate back via termios [ARM] Remove pointless casts from void pointers, [ARM] Misc minor interrupt handler cleanups [ARM] Remove at91_lcdc.h [ARM] ARRAY_SIZE() cleanup [ARM] Update mach-types * msm: [ARM] msm: dma support for MSM7X00A [ARM] msm: board file for MACH_HALIBUT (QCT MSM7200A) [ARM] msm: irq and timer support for ARCH_MSM7X00A [ARM] msm: core platform support for ARCH_MSM7X00A * s3c2410: (33 commits) [ARM] 4795/1: S3C244X: Add armclk and setparent call [ARM] 4794/1: S3C24XX: Comonise S3C2440 and S3C2442 clock code [ARM] 4793/1: S3C24XX: Add IRQ->GPIO pin mapping function [ARM] 4792/1: S3C24XX: Remove warnings from debug-macro.S [ARM] 4791/1: S3C2412: Make fclk a parent of msysclk [ARM] 4790/1: S3C2412: Fix parent selection for msysclk. [ARM] 4789/1: S3C2412: Add missing CLKDIVN register values [ARM] 4788/1: S3C24XX: Fix paramet to s3c2410_dma_ctrl if S3C2410_DMAF_AUTOSTART used. [ARM] 4787/1: S3C24XX: s3c2410_dma_request() should return the allocated channel number [ARM] 4786/1: S3C2412: Add SPI FIFO controll constants [ARM] 4785/1: S3C24XX: Add _SHIFT definitions for S3C2410_BANKCON registers [ARM] 4784/1: S3C24XX: Fix GPIO restore glitches [ARM] 4783/1: S3C24XX: Add s3c2410_gpio_getpull() [ARM] 4782/1: S3C24XX: Define FIQ_START for any FIQ users [ARM] 4781/1: S3C24XX: DMA suspend and resume support [ARM] 4780/1: S3C2412: Allow for seperate DMA channels for TX and RX [ARM] 4779/1: S3C2412: Add s3c2412_gpio_set_sleepcfg() call [ARM] 4778/1: S3C2412: Add armclk and init from DVS state [ARM] 4777/1: S3C24XX: Ensure clk_set_rate() checks the set_rate method for the clk [ARM] 4775/1: s3c2410: fix compilation error if only s3c2442 cpu is selected ... * sa1100: [ARM] sa1100: add clock source support * vfp: [ARM] 4584/2: ARMv7: Add Advanced SIMD (NEON) extension support [ARM] 4583/1: ARMv7: Add VFPv3 support [ARM] 4582/2: Add support for the common VFP subarchitecture
This commit is contained in:
Russell King
committed by
Russell King
Russell King
@@ -1,148 +0,0 @@
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/*
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* include/asm-arm/arch-at91/at91_lcdc.h
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*
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* LCD Controller (LCDC).
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* Based on AT91SAM9261 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_LCDC_H
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#define AT91_LCDC_H
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#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
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#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
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#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
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#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
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#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
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#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
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#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
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#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
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#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
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#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
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#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
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#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
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#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
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#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
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#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
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#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
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#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
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#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
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#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
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#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
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#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
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#define AT91_LCDC_DISTYPE_TFT (2 << 0)
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#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
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#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
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#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
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#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
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#define AT91_LCDC_IFWIDTH_4 (0 << 3)
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#define AT91_LCDC_IFWIDTH_8 (1 << 3)
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#define AT91_LCDC_IFWIDTH_16 (2 << 3)
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#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
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#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
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#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
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#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
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#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
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#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
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#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
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#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
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#define AT91_LCDC_INVVD_NORMAL (0 << 8)
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#define AT91_LCDC_INVVD_INVERTED (1 << 8)
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#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
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#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
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#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
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#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
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#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
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#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
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#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
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#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
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#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
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#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
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#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
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#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
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#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
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#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
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#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
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#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
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#define AT91_LCDC_MEMOR_BIG (0 << 31)
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#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
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#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
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#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
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#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
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#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
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#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
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#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
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#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
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#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
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#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
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#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
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#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
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#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
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#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
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#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
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#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
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#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
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#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
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#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
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#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
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#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
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#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
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#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
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#define AT91_LCDC_DP1_2_VAL (0xff)
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#define AT91_LCDC_DP4_7_VAL (0xfffffff)
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#define AT91_LCDC_DP3_5_VAL (0xfffff)
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#define AT91_LCDC_DP2_3_VAL (0xfff)
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#define AT91_LCDC_DP5_7_VAL (0xfffffff)
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#define AT91_LCDC_DP3_4_VAL (0xffff)
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#define AT91_LCDC_DP4_5_VAL (0xfffff)
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#define AT91_LCDC_DP6_7_VAL (0xfffffff)
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#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
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#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
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#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
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#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
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#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
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#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
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#define AT91_LCDC_PS_DIV1 (0 << 0)
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#define AT91_LCDC_PS_DIV2 (1 << 0)
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#define AT91_LCDC_PS_DIV4 (2 << 0)
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#define AT91_LCDC_PS_DIV8 (3 << 0)
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#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
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#define AT91_LCDC_POL_NEGATIVE (0 << 2)
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#define AT91_LCDC_POL_POSITIVE (1 << 2)
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#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
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#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
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#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
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#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
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#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
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#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
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#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
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#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
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#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
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#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
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#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
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#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
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#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
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#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
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#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
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#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
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#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
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#endif
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@@ -25,6 +25,7 @@
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
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#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
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#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
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#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
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@@ -37,7 +38,9 @@
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#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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@@ -52,6 +55,10 @@
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
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#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
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#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
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#define AT91_PMC_USBDIV_1 (0 << 28)
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#define AT91_PMC_USBDIV_2 (1 << 28)
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#define AT91_PMC_USBDIV_4 (2 << 28)
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
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#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
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@@ -13,19 +13,19 @@
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#ifndef AT91_RTT_H
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#define AT91_RTT_H
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#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
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#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
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#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
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#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
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#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
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#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
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#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
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#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
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#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
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#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
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#define AT91_RTT_VR 0x08 /* Real-time Value Register */
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#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
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#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
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#define AT91_RTT_SR 0x0c /* Real-time Status Register */
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#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
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#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
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@@ -21,6 +21,8 @@
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#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
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#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
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#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
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#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */
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#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */
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#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
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#define AT91_TWI_MMR 0x04 /* Master Mode Register */
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@@ -32,6 +34,9 @@
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#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
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#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
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#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */
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#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */
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#define AT91_TWI_IADR 0x0c /* Internal Address Register */
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#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
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@@ -43,9 +48,15 @@
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#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
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#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
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#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
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#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */
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#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */
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#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */
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#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
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#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
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#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
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#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */
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#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */
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#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */
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#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
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#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
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@@ -0,0 +1,121 @@
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/*
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* include/asm-arm/arch-at91/at91cap9.h
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*
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* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Common definitions.
|
||||
* Based on AT91CAP9 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91CAP9_H
|
||||
#define AT91CAP9_H
|
||||
|
||||
/*
|
||||
* Peripheral identifiers/interrupts.
|
||||
*/
|
||||
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
|
||||
#define AT91_ID_SYS 1 /* System Peripherals */
|
||||
#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
|
||||
#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
|
||||
#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
|
||||
#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
|
||||
#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
|
||||
#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
|
||||
#define AT91CAP9_ID_US0 8 /* USART 0 */
|
||||
#define AT91CAP9_ID_US1 9 /* USART 1 */
|
||||
#define AT91CAP9_ID_US2 10 /* USART 2 */
|
||||
#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
|
||||
#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
|
||||
#define AT91CAP9_ID_CAN 13 /* CAN */
|
||||
#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
|
||||
#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
|
||||
#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
|
||||
#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
|
||||
#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
|
||||
#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
|
||||
#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
|
||||
#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
|
||||
#define AT91CAP9_ID_EMAC 22 /* Ethernet */
|
||||
#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
|
||||
#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
|
||||
#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
|
||||
#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
|
||||
#define AT91CAP9_ID_DMA 27 /* DMA Controller */
|
||||
#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
|
||||
#define AT91CAP9_ID_UHP 29 /* USB Host Port */
|
||||
#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
|
||||
#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
|
||||
|
||||
/*
|
||||
* User Peripheral physical base addresses.
|
||||
*/
|
||||
#define AT91CAP9_BASE_UDPHS 0xfff78000
|
||||
#define AT91CAP9_BASE_TCB0 0xfff7c000
|
||||
#define AT91CAP9_BASE_TC0 0xfff7c000
|
||||
#define AT91CAP9_BASE_TC1 0xfff7c040
|
||||
#define AT91CAP9_BASE_TC2 0xfff7c080
|
||||
#define AT91CAP9_BASE_MCI0 0xfff80000
|
||||
#define AT91CAP9_BASE_MCI1 0xfff84000
|
||||
#define AT91CAP9_BASE_TWI 0xfff88000
|
||||
#define AT91CAP9_BASE_US0 0xfff8c000
|
||||
#define AT91CAP9_BASE_US1 0xfff90000
|
||||
#define AT91CAP9_BASE_US2 0xfff94000
|
||||
#define AT91CAP9_BASE_SSC0 0xfff98000
|
||||
#define AT91CAP9_BASE_SSC1 0xfff9c000
|
||||
#define AT91CAP9_BASE_AC97C 0xfffa0000
|
||||
#define AT91CAP9_BASE_SPI0 0xfffa4000
|
||||
#define AT91CAP9_BASE_SPI1 0xfffa8000
|
||||
#define AT91CAP9_BASE_CAN 0xfffac000
|
||||
#define AT91CAP9_BASE_PWMC 0xfffb8000
|
||||
#define AT91CAP9_BASE_EMAC 0xfffbc000
|
||||
#define AT91CAP9_BASE_ADC 0xfffc0000
|
||||
#define AT91CAP9_BASE_ISI 0xfffc4000
|
||||
#define AT91_BASE_SYS 0xffffe200
|
||||
|
||||
/*
|
||||
* System Peripherals (offset from AT91_BASE_SYS)
|
||||
*/
|
||||
#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
|
||||
#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
|
||||
#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
|
||||
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
|
||||
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
|
||||
#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
|
||||
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
|
||||
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
|
||||
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
|
||||
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
|
||||
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
|
||||
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
|
||||
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
|
||||
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
|
||||
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
|
||||
#define AT91_SHDC (0xfffffd10 - AT91_BASE_SYS)
|
||||
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
|
||||
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
|
||||
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
|
||||
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
|
||||
|
||||
/*
|
||||
* Internal Memory.
|
||||
*/
|
||||
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
|
||||
#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
|
||||
|
||||
#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
|
||||
#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
|
||||
|
||||
#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
|
||||
#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
|
||||
#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
|
||||
|
||||
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,132 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91/at91cap9_matrix.h
|
||||
*
|
||||
* Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
|
||||
* Copyright (C) 2006 Atmel Corporation.
|
||||
*
|
||||
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
|
||||
* Based on AT91CAP9 datasheet revision B (Preliminary).
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91CAP9_MATRIX_H
|
||||
#define AT91CAP9_MATRIX_H
|
||||
|
||||
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
|
||||
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
|
||||
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
|
||||
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
|
||||
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
|
||||
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
|
||||
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
|
||||
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
|
||||
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
|
||||
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
|
||||
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
|
||||
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
|
||||
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
|
||||
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
|
||||
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
|
||||
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
|
||||
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
|
||||
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
|
||||
|
||||
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
|
||||
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
|
||||
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
|
||||
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
|
||||
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
|
||||
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
|
||||
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
|
||||
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
|
||||
#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
|
||||
#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
|
||||
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
|
||||
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
|
||||
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
|
||||
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
|
||||
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
|
||||
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
|
||||
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
|
||||
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
|
||||
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
|
||||
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
|
||||
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
|
||||
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
|
||||
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
|
||||
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
|
||||
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
|
||||
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
|
||||
#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
|
||||
#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
|
||||
#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
|
||||
#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
|
||||
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
|
||||
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
|
||||
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
|
||||
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
|
||||
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
|
||||
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
|
||||
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
|
||||
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
|
||||
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
|
||||
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
|
||||
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_MATRIX_RCB2 (1 << 2)
|
||||
#define AT91_MATRIX_RCB3 (1 << 3)
|
||||
#define AT91_MATRIX_RCB4 (1 << 4)
|
||||
#define AT91_MATRIX_RCB5 (1 << 5)
|
||||
#define AT91_MATRIX_RCB6 (1 << 6)
|
||||
#define AT91_MATRIX_RCB7 (1 << 7)
|
||||
#define AT91_MATRIX_RCB8 (1 << 8)
|
||||
#define AT91_MATRIX_RCB9 (1 << 9)
|
||||
#define AT91_MATRIX_RCB10 (1 << 10)
|
||||
#define AT91_MATRIX_RCB11 (1 << 11)
|
||||
|
||||
#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
|
||||
#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
|
||||
|
||||
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
|
||||
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
|
||||
#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
|
||||
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
|
||||
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
|
||||
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
|
||||
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
|
||||
|
||||
#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
|
||||
#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
|
||||
#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
|
||||
|
||||
#endif
|
||||
@@ -67,7 +67,7 @@
|
||||
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
|
||||
#define AT91_MATRIX_CS4A_SMC (0 << 4)
|
||||
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
|
||||
#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
|
||||
#define AT91_MATRIX_CS5A_SMC (0 << 5)
|
||||
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
|
||||
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
@@ -38,7 +38,7 @@
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
|
||||
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
|
||||
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
|
||||
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
|
||||
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
|
||||
|
||||
@@ -34,6 +34,7 @@
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
/* USB Device */
|
||||
@@ -71,7 +72,7 @@ struct at91_eth_data {
|
||||
};
|
||||
extern void __init at91_add_device_eth(struct at91_eth_data *data);
|
||||
|
||||
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263)
|
||||
#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
|
||||
#define eth_platform_data at91_eth_data
|
||||
#endif
|
||||
|
||||
@@ -101,13 +102,23 @@ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_de
|
||||
extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
|
||||
|
||||
/* Serial */
|
||||
#define ATMEL_UART_CTS 0x01
|
||||
#define ATMEL_UART_RTS 0x02
|
||||
#define ATMEL_UART_DSR 0x04
|
||||
#define ATMEL_UART_DTR 0x08
|
||||
#define ATMEL_UART_DCD 0x10
|
||||
#define ATMEL_UART_RI 0x20
|
||||
|
||||
extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
|
||||
extern void __init at91_set_serial_console(unsigned portnr);
|
||||
|
||||
struct at91_uart_config {
|
||||
unsigned short console_tty; /* tty number of serial console */
|
||||
unsigned short nr_tty; /* number of serial tty's */
|
||||
short tty_map[]; /* map UART to tty number */
|
||||
};
|
||||
extern struct platform_device *atmel_default_console_device;
|
||||
extern void __init at91_init_serial(struct at91_uart_config *config);
|
||||
extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
|
||||
|
||||
struct atmel_uart_data {
|
||||
short use_dma_tx; /* use transmit DMA? */
|
||||
@@ -116,6 +127,23 @@ struct atmel_uart_data {
|
||||
};
|
||||
extern void __init at91_add_device_serial(void);
|
||||
|
||||
/*
|
||||
* SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
|
||||
* platform devices. Their SSC ID is part of their configuration data,
|
||||
* along with information about which SSC signals they should use.
|
||||
*/
|
||||
#define ATMEL_SSC_TK 0x01
|
||||
#define ATMEL_SSC_TF 0x02
|
||||
#define ATMEL_SSC_TD 0x04
|
||||
#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
|
||||
|
||||
#define ATMEL_SSC_RK 0x10
|
||||
#define ATMEL_SSC_RF 0x20
|
||||
#define ATMEL_SSC_RD 0x40
|
||||
#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
|
||||
|
||||
extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
|
||||
|
||||
/* LCD Controller */
|
||||
struct atmel_lcdfb_info;
|
||||
extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
|
||||
@@ -126,10 +154,12 @@ struct atmel_ac97_data {
|
||||
};
|
||||
extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
|
||||
|
||||
/* ISI */
|
||||
extern void __init at91_add_device_isi(void);
|
||||
|
||||
/* LEDs */
|
||||
extern u8 at91_leds_cpu;
|
||||
extern u8 at91_leds_timer;
|
||||
extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
|
||||
extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
|
||||
|
||||
/* FIXME: this needs a better location, but gets stuff building again */
|
||||
extern int at91_suspend_entering_slow_clock(void);
|
||||
|
||||
@@ -21,13 +21,13 @@
|
||||
#define ARCH_ID_AT91SAM9260 0x019803a0
|
||||
#define ARCH_ID_AT91SAM9261 0x019703a0
|
||||
#define ARCH_ID_AT91SAM9263 0x019607a0
|
||||
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
|
||||
#define ARCH_ID_AT91CAP9 0x039A03A0
|
||||
|
||||
#define ARCH_ID_AT91SAM9XE128 0x329973a0
|
||||
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
|
||||
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
|
||||
|
||||
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
|
||||
|
||||
#define ARCH_ID_AT91M40800 0x14080044
|
||||
#define ARCH_ID_AT91R40807 0x44080746
|
||||
#define ARCH_ID_AT91M40807 0x14080745
|
||||
@@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
|
||||
#define cpu_is_at91sam9rl() (0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_AT91CAP9
|
||||
#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
|
||||
#else
|
||||
#define cpu_is_at91cap9() (0)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Since this is ARM, we will never run on any AVR32 CPU. But these
|
||||
|
||||
@@ -17,13 +17,13 @@
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_preamble, base, tmp
|
||||
ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
|
||||
.endm
|
||||
|
||||
.macro arch_ret_to_user, tmp1, tmp2
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
|
||||
ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
|
||||
ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
|
||||
teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
|
||||
|
||||
@@ -26,6 +26,8 @@
|
||||
#include <asm/arch/at91sam9263.h>
|
||||
#elif defined(CONFIG_ARCH_AT91SAM9RL)
|
||||
#include <asm/arch/at91sam9rl.h>
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
#include <asm/arch/at91cap9.h>
|
||||
#elif defined(CONFIG_ARCH_AT91X40)
|
||||
#include <asm/arch/at91x40.h>
|
||||
#else
|
||||
|
||||
@@ -42,6 +42,11 @@
|
||||
#define AT91SAM9_MASTER_CLOCK 100000000
|
||||
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91CAP9)
|
||||
|
||||
#define AT91CAP9_MASTER_CLOCK 100000000
|
||||
#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16)
|
||||
|
||||
#elif defined(CONFIG_ARCH_AT91X40)
|
||||
|
||||
#define AT91X40_MASTER_CLOCK 40000000
|
||||
|
||||
@@ -5,16 +5,6 @@
|
||||
#ifndef __ASM_ARCH_GPIO_H
|
||||
#define __ASM_ARCH_GPIO_H
|
||||
|
||||
#define GPIO_IN 0
|
||||
#define GPIO_OUT 1
|
||||
|
||||
#define EP93XX_GPIO_LOW 0
|
||||
#define EP93XX_GPIO_HIGH 1
|
||||
|
||||
extern void gpio_line_config(int line, int direction);
|
||||
extern int gpio_line_get(int line);
|
||||
extern void gpio_line_set(int line, int value);
|
||||
|
||||
/* GPIO port A. */
|
||||
#define EP93XX_GPIO_LINE_A(x) ((x) + 0)
|
||||
#define EP93XX_GPIO_LINE_EGPIO0 EP93XX_GPIO_LINE_A(0)
|
||||
@@ -38,7 +28,7 @@ extern void gpio_line_set(int line, int value);
|
||||
#define EP93XX_GPIO_LINE_EGPIO15 EP93XX_GPIO_LINE_B(7)
|
||||
|
||||
/* GPIO port C. */
|
||||
#define EP93XX_GPIO_LINE_C(x) ((x) + 16)
|
||||
#define EP93XX_GPIO_LINE_C(x) ((x) + 40)
|
||||
#define EP93XX_GPIO_LINE_ROW0 EP93XX_GPIO_LINE_C(0)
|
||||
#define EP93XX_GPIO_LINE_ROW1 EP93XX_GPIO_LINE_C(1)
|
||||
#define EP93XX_GPIO_LINE_ROW2 EP93XX_GPIO_LINE_C(2)
|
||||
@@ -71,7 +61,7 @@ extern void gpio_line_set(int line, int value);
|
||||
#define EP93XX_GPIO_LINE_IDEDA2 EP93XX_GPIO_LINE_E(7)
|
||||
|
||||
/* GPIO port F. */
|
||||
#define EP93XX_GPIO_LINE_F(x) ((x) + 40)
|
||||
#define EP93XX_GPIO_LINE_F(x) ((x) + 16)
|
||||
#define EP93XX_GPIO_LINE_WP EP93XX_GPIO_LINE_F(0)
|
||||
#define EP93XX_GPIO_LINE_MCCD1 EP93XX_GPIO_LINE_F(1)
|
||||
#define EP93XX_GPIO_LINE_MCCD2 EP93XX_GPIO_LINE_F(2)
|
||||
@@ -103,5 +93,49 @@ extern void gpio_line_set(int line, int value);
|
||||
#define EP93XX_GPIO_LINE_DD6 EP93XX_GPIO_LINE_H(6)
|
||||
#define EP93XX_GPIO_LINE_DD7 EP93XX_GPIO_LINE_H(7)
|
||||
|
||||
/* maximum value for gpio line identifiers */
|
||||
#define EP93XX_GPIO_LINE_MAX EP93XX_GPIO_LINE_H(7)
|
||||
|
||||
/* maximum value for irq capable line identifiers */
|
||||
#define EP93XX_GPIO_LINE_MAX_IRQ EP93XX_GPIO_LINE_F(7)
|
||||
|
||||
/* new generic GPIO API - see Documentation/gpio.txt */
|
||||
|
||||
static inline int gpio_request(unsigned gpio, const char *label)
|
||||
{
|
||||
if (gpio > EP93XX_GPIO_LINE_MAX)
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void gpio_free(unsigned gpio)
|
||||
{
|
||||
}
|
||||
|
||||
int gpio_direction_input(unsigned gpio);
|
||||
int gpio_direction_output(unsigned gpio, int value);
|
||||
int gpio_get_value(unsigned gpio);
|
||||
void gpio_set_value(unsigned gpio, int value);
|
||||
|
||||
#include <asm-generic/gpio.h> /* cansleep wrappers */
|
||||
|
||||
/*
|
||||
* Map GPIO A0..A7 (0..7) to irq 64..71,
|
||||
* B0..B7 (7..15) to irq 72..79, and
|
||||
* F0..F7 (16..24) to irq 80..87.
|
||||
*/
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
if (gpio <= EP93XX_GPIO_LINE_MAX_IRQ)
|
||||
return 64 + gpio;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned irq)
|
||||
{
|
||||
return irq - gpio_to_irq(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -67,12 +67,6 @@
|
||||
#define IRQ_EP93XX_SAI 60
|
||||
#define EP93XX_VIC2_VALID_IRQ_MASK 0x1fffffff
|
||||
|
||||
/*
|
||||
* Map GPIO A0..A7 to irq 64..71, B0..B7 to 72..79, and
|
||||
* F0..F7 to 80..87.
|
||||
*/
|
||||
#define IRQ_EP93XX_GPIO(x) (64 + (((x) + (((x) >> 2) & 8)) & 0x1f))
|
||||
|
||||
#define NR_EP93XX_IRQS (64 + 24)
|
||||
|
||||
#define EP93XX_BOARD_IRQ(x) (NR_EP93XX_IRQS + (x))
|
||||
|
||||
@@ -61,13 +61,13 @@ __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
|
||||
if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
|
||||
return __arm_ioremap(addr, size, mtype);
|
||||
|
||||
return (void *)addr;
|
||||
return (void __iomem *)addr;
|
||||
}
|
||||
|
||||
static inline void
|
||||
__ixp4xx_iounmap(void __iomem *addr)
|
||||
{
|
||||
if ((u32)addr >= VMALLOC_START)
|
||||
if ((__force u32)addr >= VMALLOC_START)
|
||||
__iounmap(addr);
|
||||
}
|
||||
|
||||
@@ -141,9 +141,9 @@ __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
|
||||
static inline void
|
||||
__ixp4xx_writel(u32 value, volatile void __iomem *p)
|
||||
{
|
||||
u32 addr = (u32)p;
|
||||
u32 addr = (__force u32)p;
|
||||
if (addr >= VMALLOC_START) {
|
||||
__raw_writel(value, addr);
|
||||
__raw_writel(value, p);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -208,11 +208,11 @@ __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
|
||||
static inline unsigned long
|
||||
__ixp4xx_readl(const volatile void __iomem *p)
|
||||
{
|
||||
u32 addr = (u32)p;
|
||||
u32 addr = (__force u32)p;
|
||||
u32 data;
|
||||
|
||||
if (addr >= VMALLOC_START)
|
||||
return __raw_readl(addr);
|
||||
return __raw_readl(p);
|
||||
|
||||
if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
|
||||
return 0xffffffff;
|
||||
@@ -438,7 +438,7 @@ __ixp4xx_ioread32(const void __iomem *addr)
|
||||
return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
|
||||
else {
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
return le32_to_cpu(__raw_readl((u32)port));
|
||||
return le32_to_cpu((__force __le32)__raw_readl(addr));
|
||||
#else
|
||||
return (unsigned int)__ixp4xx_readl(addr);
|
||||
#endif
|
||||
@@ -523,7 +523,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr)
|
||||
__ixp4xx_outl(value, port & PIO_MASK);
|
||||
else
|
||||
#ifndef CONFIG_IXP4XX_INDIRECT_PCI
|
||||
__raw_writel(cpu_to_le32(value), port);
|
||||
__raw_writel((u32 __force)cpu_to_le32(value), addr);
|
||||
#else
|
||||
__ixp4xx_writel(value, addr);
|
||||
#endif
|
||||
|
||||
@@ -49,5 +49,7 @@
|
||||
#define IOPC_TM_FALLING (4) /* Falling Edge Detection */
|
||||
#define IOPC_TM_EDGE (6) /* Both Edge Detection */
|
||||
|
||||
/* Port Data Register */
|
||||
#define IOPD_(x) (1 << (x)) /* Signal Level of GPIO Pin x */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
/* linux/include/asm-arm/arch-msm/board.h
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Author: Brian Swetland <swetland@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MSM_BOARD_H
|
||||
#define __ASM_ARCH_MSM_BOARD_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* platform device data structures */
|
||||
|
||||
struct msm_mddi_platform_data
|
||||
{
|
||||
void (*panel_power)(int on);
|
||||
unsigned has_vsync_irq:1;
|
||||
};
|
||||
|
||||
/* common init routines for use by arch/arm/mach-msm/board-*.c */
|
||||
|
||||
void __init msm_add_devices(void);
|
||||
void __init msm_map_common_io(void);
|
||||
void __init msm_init_irq(void);
|
||||
void __init msm_init_gpio(void);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
/* include/asm-arm/arch-msm7200/debug-macro.S
|
||||
*
|
||||
* Copyright (C) 2007 Google, Inc.
|
||||
* Author: Brian Swetland <swetland@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/arch/msm_iomap.h>
|
||||
|
||||
.macro addruart,rx
|
||||
@ see if the MMU is enabled and select appropriate base address
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1
|
||||
ldreq \rx, =MSM_UART1_PHYS
|
||||
ldrne \rx, =MSM_UART1_BASE
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
str \rd, [\rx, #0x0C]
|
||||
.endm
|
||||
|
||||
.macro waituart,rd,rx
|
||||
@ wait for TX_READY
|
||||
1: ldr \rd, [\rx, #0x08]
|
||||
tst \rd, #0x04
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
.macro busyuart,rd,rx
|
||||
.endm
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user