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434 lines
19 KiB
C
434 lines
19 KiB
C
//-----------------------------------------------------------------------------
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// Copyright (C) Jonathan Westhues, Sept 2005
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// Copyright (C) Proxmark3 contributors. See AUTHORS.md for details.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// See LICENSE.txt for the text of the license.
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//-----------------------------------------------------------------------------
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// Timers, Clocks functions used in LF or Legic where you would need detailed time.
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//-----------------------------------------------------------------------------
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#include "ticks_apis.h"
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#include "proxmark3_arm.h"
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#include "ticks_hw_at32.h"
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#include "at32f435_437.h"
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#include "at32f435_437_misc.h"
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#include "at32f435_437_pwc.h"
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#include "at32f435_437_ertc.h"
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/**
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* SysTick 频率计算，以下计算条件需要严格遵守 AHBCLK = 288mhz 且 systick的时钟输入是 AHBCLK 的8分频的条件
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*
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* - AHBCLK = 288,000, 000 = 288mhz
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* - systick-clk = 288mhz / 8 = 36,000,000 = 36mhz = 27.7ns
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* - systick-val = 24bit = 0xFFFFFF = 16777215
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* - max time = 27.7ns * 16777215 = 464,728.8555us = 464.7288555ms
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*/
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#define MAX_US_STEP (464728U)
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// timer counts in 27.7ns increments (16777215/36MHz), rounding applies
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// WARNING: timer can't measure more than 1.39s (27.7ns * 0xFFFFFF * 3), more loop delay may to decreased accuracy.
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void SpinDelayUs(int us) {
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uint32_t fac_us = system_core_clock / 8 / 1000000;
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uint32_t temp = 0;
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SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV; // ahbclk div8 = 36mhz
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while (us) {
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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if (us > MAX_US_STEP) {
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SysTick->LOAD = MAX_US_STEP * fac_us;
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us -= MAX_US_STEP;
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} else {
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SysTick->LOAD = us * fac_us;
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us = 0;
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}
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SysTick->VAL = 0x00;
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SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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do {
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temp = SysTick->CTRL;
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} while ((temp & 0x01) && !(temp & (1 << 16)));
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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SysTick->VAL = 0x00;
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}
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}
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// configCounter() is defined below (outside AS_BOOTROM); forward-declare it so the
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// precision/timestamp counters inside the AS_BOOTROM block can reuse it.
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static void configCounter(const uint32_t frequency);
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#ifndef AS_BOOTROM
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// timer counts in 27.7ns increments (16777215/36MHz), rounding applies
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// WARNING: timer can't measure more than 464.7288555ms (27.7ns * 0xFFFFFF)
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void SpinDelayUsPrecision(int us) {
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uint32_t fac_us = system_core_clock / 8 / 1000000;
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uint32_t temp = 0;
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV; // ahbclk div8 = 36mhz
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SysTick->VAL = 0x00;
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SysTick->LOAD = us * fac_us;
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SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
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do {
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temp = SysTick->CTRL;
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} while ((temp & 0x01) && !(temp & (1 << 16)));
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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SysTick->VAL = 0x00;
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}
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// -------------------------------------------------------------------------
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// Timer lib: 1 kHz: TickCount functions
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//
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// Precision Test Procedure:
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// ti = GetTickCount();
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// SpinDelay(1000);
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// ti = GetTickCount() - ti;
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// Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
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// -------------------------------------------------------------------------
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// Cached tick start value when 'StartTickCount' call.
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static volatile uint64_t tick_start_val;
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// from date to timestamp(unix format, UTC zone only)
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// we can use 'mktime()' from 'time.h', but more rom space required, so custom first.
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// tips: year is full length, such as: 2025, not 25
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static uint64_t mktime_utc_fast(int year, int month, int day, int hour, int minute, int second, uint32_t ms) {
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static const uint16_t cum_days[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334};
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int years = year - 1970;
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int leap_count = (years + 2) / 4;
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if (year > 2100) leap_count--;
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if (year > 2200) leap_count--;
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if (year > 2300) leap_count--;
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uint64_t days = years * 365ULL + leap_count;
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days += cum_days[month - 1];
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if (month > 2 && ((year % 4 == 0 && year % 100 != 0) || (year % 400 == 0))) {
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days++;
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}
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days += (day - 1);
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return (days * 86400ULL + hour * 3600ULL + minute * 60ULL + second) * 1000ULL + ms;
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}
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// Start tick count
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void StartTickCount(void) {
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UpdateTickCountLabel();
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crm_periph_clock_enable(CRM_PWC_PERIPH_CLOCK, TRUE); // enable the pwc clock
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pwc_battery_powered_domain_access(TRUE); // allow access to ertc
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crm_battery_powered_domain_reset(TRUE); // reset ertc bpr domain
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crm_battery_powered_domain_reset(FALSE);
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// Select clock source: HEXT = 8mhz, ertc clk = 400khz
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// When using an external high-speed crystal oscillator, the clock can be very accurate,
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// so calibration does not need to be considered temporarily.
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crm_ertc_clock_select(CRM_ERTC_CLOCK_HEXT_DIV_20);
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crm_ertc_clock_enable(TRUE); // enable the ertc clock
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ertc_reset(); // deinitializes the ertc registers
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ertc_wait_update(); // wait for ertc apb registers update
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// configure the ertc divider, ertc second(1hz) = ertc_clk / (div_a + 1) * (div_b + 1)
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// the subsecond frequency is 3125(from div_b clk), so 1 clk = 0.32ms = 320us, the subsecond will -1 every 0.32ms
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ertc_divider_set(127, 3124); // 400000 / (127 + 1) * (3124 + 1) = 1hz
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ertc_hour_mode_set(ERTC_HOUR_MODE_24); // configure the ertc hour mode
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// set datetime: 2025-08-15 13:00:00, format: YEAR-MONTH-DAY HOUR:MINUTE:SECOND
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ertc_date_set(25, 8, 15, 5); // set date
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ertc_time_set(13, 0, 0, ERTC_AM); // set time
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// update tick start value when 'poweron'
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// no need calc, we can hard code cause by 'ertc_date_set' and 'ertc_time_set' is hard code
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// calc online: https://www.timestamp-converter.com/
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tick_start_val = 1755262800000ULL; // tick_start_val = mktime_utc_fast(2025, 8, 15, 13, 0, 0, 0);
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}
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// Get the current count.
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uint32_t RAMFUNC GetTickCount(void) {
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ertc_time_type time;
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ertc_calendar_get(&time);
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return mktime_utc_fast(
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// time.year is short length, not full, so 2025 is 25.
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time.year + 2000,
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// month & day & hour & min & sec is full length
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time.month, time.day, time.hour, time.min, time.sec,
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// this ms is from 0 -> 1000 of second, not timestamp value
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// ms = ((divb + 1) - subsecond * 1000) / (divb + 1)
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(3125 - ertc_sub_second_get()) * 1000 / 3125) - tick_start_val; // current - start = tick
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}
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// -------------------------------------------------------------------------
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// Timer for iso14443 commands. Uses ssp_clk from FPGA
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// -------------------------------------------------------------------------
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void StartCountSspClk(void) {
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crm_periph_clock_enable(CRM_GPIO_PERIPH_COUNT_SSP_CLK, TRUE);
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crm_periph_clock_enable(AT32_CRM_TMR_PERIPH_COUNT_SSP_CLK, TRUE);
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// gpio init
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gpio_init_type gpio_init_struct = {0};
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_pins = CRM_GPIO_COUNT_SSP_CLK_PIN;
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gpio_init(CRM_GPIO_COUNT_SSP_CLK, &gpio_init_struct); // gpio setup
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gpio_pin_mux_config(CRM_GPIO_COUNT_SSP_CLK, CRM_GPIO_COUNT_SSP_CLK_SOURCE, CRM_GPIO_COUNT_SSP_CLK_MUX); // important !!! remap gpio to be timer EXT(CHx) function.
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// timer init
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tmr_input_config_type tmr_input_config_struct;
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tmr_input_config_struct.input_channel_select = AT32_TMR_COUNT_SSP_CLK_IN_CH;
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tmr_input_config_struct.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
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tmr_input_config_struct.input_polarity_select = TMR_INPUT_RISING_EDGE;
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tmr_input_channel_init(AT32_TMR_COUNT_SSP_CLK, &tmr_input_config_struct, TMR_CHANNEL_INPUT_DIV_1);
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tmr_trigger_input_select(AT32_TMR_COUNT_SSP_CLK, TMR_SUB_INPUT_SEL_C2DF2); // select the timer input trigger: C2IF2
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tmr_sub_mode_select(AT32_TMR_COUNT_SSP_CLK, TMR_SUB_EXTERNAL_CLOCK_MODE_A); // select the slave mode: external mode a
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tmr_32_bit_function_enable(AT32_TMR_COUNT_SSP_CLK, TRUE); // 32bit enable, reduce the complexity of cascading.
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tmr_base_init(AT32_TMR_COUNT_SSP_CLK, UINT32_MAX - 1, 0); // 288mhz, not count increment frequency.
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tmr_cnt_dir_set(AT32_TMR_COUNT_SSP_CLK, TMR_COUNT_UP);
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// tmr_external_clock_mode2_config(CRM_TMR_COUNT_SSP_CLK, TMR_ES_FREQUENCY_DIV_1, TMR_ES_POLARITY_NON_INVERTED, 0x00); ext引脚而非ch2引脚时，使用此初始化函数
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tmr_counter_enable(AT32_TMR_COUNT_SSP_CLK, TRUE);
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// TODO DXL 可能还得像原先的逻辑那样，跳过8个clock，去同步ssp的frame和时钟，因为我们没有用级联定时器这种操作，理论上
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// 可能只需要同步一次frame的上升和下降，因为在ssp-timode的实现下，frame的上升刚好是在lsb的上升沿去执行的，
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// 同步完成之后，理论上下一次clk的上升刚好就是下一帧的msb，这个时候重置一下clk值就刚好是新的一次帧计数？不过，这还不好说，具体得看后续的实现。
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}
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void ResetSspClk(void) {
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// tmr_counter_value_set(CRM_TMR_COUNT_SSP_CLK, 0);
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AT32_TMR_COUNT_SSP_CLK->cval = 0;
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}
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uint32_t RAMFUNC GetCountSspClk(void) {
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// return tmr_counter_value_get(CRM_TMR_COUNT_SSP_CLK);
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return AT32_TMR_COUNT_SSP_CLK->cval;
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}
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// -------------------------------------------------------------------------
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// Precision counter, input capture and timestamp counter.
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// See ticks_apis.h for the generic contract. Both the precision counter and
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// the timestamp counter run at 1.5 MHz (12 counts = 1 T0 = 8 us).
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// -------------------------------------------------------------------------
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// Timestamp counter overflow count, combined for ~47 min timing.
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static uint16_t timestamp_high = 0;
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void StartPrecisionCounter(void) {
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// Reuses the 32-bit timer @ 1.5 MHz (same source as StartTicks).
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configCounter(1500000);
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}
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void StopPrecisionCounter(void) {
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tmr_counter_enable(AT32_TMR_PRECISE_COUNTER, FALSE);
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}
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void ResetPrecisionCounter(void) {
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tmr_counter_value_set(AT32_TMR_PRECISE_COUNTER, 0);
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}
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uint16_t RAMFUNC GetPrecisionCounter(void) {
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return (uint16_t)tmr_counter_value_get(AT32_TMR_PRECISE_COUNTER);
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}
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// The free running counter itself, and the distance from a captured value.
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//
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// Declared in ticks_apis.h and used by the Hitag paths, which need a reference
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// they can subtract from rather than a value relative to the last reset. These
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// were added for AT91 without an AT32 counterpart, which left the PM5 build
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// failing to link with undefined references to both.
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uint16_t RAMFUNC GetPrecisionCounterRaw(void) {
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return (uint16_t)tmr_counter_value_get(AT32_TMR_PRECISE_COUNTER);
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}
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uint16_t RAMFUNC GetPrecisionCounterDelta(uint16_t start) {
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return (uint16_t)((uint16_t)tmr_counter_value_get(AT32_TMR_PRECISE_COUNTER) - start);
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}
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void StartLoEdgeCapture(void) {
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crm_periph_clock_enable(CRM_GPIO_PERIPH_INPUT_CAPTURE, TRUE);
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crm_periph_clock_enable(AT32_CRM_TMR_PERIPH_INPUT_CAPTURE, TRUE);
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// GPIO: PB4 -> TMR3_CH1 (input capture on the LF SSC frame signal).
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gpio_init_type gpio_init_struct = {0};
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gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
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gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
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gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
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gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
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gpio_init_struct.gpio_pins = CRM_GPIO_INPUT_CAPTURE_PIN;
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gpio_init(CRM_GPIO_INPUT_CAPTURE, &gpio_init_struct); // gpio setup
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gpio_pin_mux_config(CRM_GPIO_INPUT_CAPTURE, CRM_GPIO_INPUT_CAPTURE_SOURCE, CRM_GPIO_INPUT_CAPTURE_MUX); // remap gpio to TMR3_CH1
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// Time base: 16-bit counter @ 1.5 MHz (TIMER_CLK / (191 + 1) = 288MHz / 192),
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// matching the AT91 TC1 (MCK/32) so that 12 counts = 1 T0 = 8 us.
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tmr_reset(AT32_TMR_INPUT_CAPTURE);
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tmr_base_init(AT32_TMR_INPUT_CAPTURE, UINT16_MAX, 191);
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tmr_cnt_dir_set(AT32_TMR_INPUT_CAPTURE, TMR_COUNT_UP);
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// PWM input mode (dual-edge capture) on CH1 (TI1 = PB4):
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// CH1 = direct + falling edge, CH2 = indirect (chained from TI1) + rising edge.
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tmr_input_config_type ic = {0};
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ic.input_channel_select = TMR_SELECT_CHANNEL_1;
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ic.input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
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ic.input_polarity_select = TMR_INPUT_FALLING_EDGE;
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tmr_pwm_input_config(AT32_TMR_INPUT_CAPTURE, &ic, TMR_CHANNEL_INPUT_DIV_1);
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// Slave reset mode: reset the counter on the CH1 (falling) edge, so C1DT holds
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// the period since the previous falling edge (matches AT91 ABETRG + ETRGEDG_FALLING).
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tmr_trigger_input_select(AT32_TMR_INPUT_CAPTURE, TMR_SUB_INPUT_SEL_C1DF1);
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tmr_sub_mode_select(AT32_TMR_INPUT_CAPTURE, TMR_SUB_RESET_MODE);
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tmr_sub_sync_mode_set(AT32_TMR_INPUT_CAPTURE, TRUE);
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tmr_counter_value_set(AT32_TMR_INPUT_CAPTURE, 0);
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tmr_counter_enable(AT32_TMR_INPUT_CAPTURE, TRUE);
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}
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void StopLoEdgeCapture(void) {
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tmr_counter_enable(AT32_TMR_INPUT_CAPTURE, FALSE);
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}
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void EnableLoEdgeCapture(void) {
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tmr_counter_value_set(AT32_TMR_INPUT_CAPTURE, 0);
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tmr_counter_enable(AT32_TMR_INPUT_CAPTURE, TRUE);
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}
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void ResetLoEdgeCapture(void) {
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tmr_counter_value_set(AT32_TMR_INPUT_CAPTURE, 0);
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}
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uint16_t RAMFUNC GetLoEdgeCaptureCount(void) {
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return (uint16_t)tmr_counter_value_get(AT32_TMR_INPUT_CAPTURE);
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}
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uint16_t RAMFUNC GetLoEdgeCaptureFalling(void) {
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// The falling-edge value is captured on CH1 (C1DT).
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return (uint16_t)tmr_channel_value_get(AT32_TMR_INPUT_CAPTURE, TMR_SELECT_CHANNEL_1);
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}
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uint16_t RAMFUNC GetLoEdgeCaptureRising(void) {
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// The rising-edge value is captured on CH2 (C2DT).
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return (uint16_t)tmr_channel_value_get(AT32_TMR_INPUT_CAPTURE, TMR_SELECT_CHANNEL_2);
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}
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lo_edge_t RAMFUNC GetLoEdgeCaptureStatus(void) {
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// Reading the status clears the edge-event flags (matches AT91 TC_SR semantics).
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uint32_t ists = AT32_TMR_INPUT_CAPTURE->ists;
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// Only clear the overflow flag if it is set, to avoid clearing the edge-event flags.
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if (ists & TMR_OVF_FLAG) {
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// Clear the overflow flag to avoid repeated interrupts.
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AT32_TMR_INPUT_CAPTURE->ists = ~TMR_OVF_FLAG;
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}
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if (ists & INPUT_CAPTURE_EVT_RISING_EDGE) {
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AT32_TMR_INPUT_CAPTURE->ists = ~INPUT_CAPTURE_EVT_RISING_EDGE;
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return LO_EDGE_RISING;
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}
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if (ists & INPUT_CAPTURE_EVT_FALLING_EDGE) {
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AT32_TMR_INPUT_CAPTURE->ists = ~INPUT_CAPTURE_EVT_FALLING_EDGE;
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return LO_EDGE_FALLING;
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}
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return LO_EDGE_NO;
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}
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void StartTimestamp(void) {
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// TMR6: basic 16-bit timer, free-running @ 1.5 MHz.
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crm_periph_clock_enable(AT32_CRM_TMR_PERIPH_TIMESTAMP, TRUE);
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// APB1 = 144 MHz, divX = (144 MHz / 1.5 MHz) * 2 - 1 = 191 (see configCounter()).
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tmr_base_init(AT32_TMR_TIMESTAMP, UINT16_MAX, 191);
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tmr_cnt_dir_set(AT32_TMR_TIMESTAMP, TMR_COUNT_UP);
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tmr_counter_value_set(AT32_TMR_TIMESTAMP, 0);
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tmr_counter_enable(AT32_TMR_TIMESTAMP, TRUE);
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timestamp_high = 0;
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}
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void StopTimestamp(void) {
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tmr_counter_enable(AT32_TMR_TIMESTAMP, FALSE);
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}
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uint32_t RAMFUNC GetTimestamp(void) {
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// Sample the counter on both sides of the overflow check, so a wrap that
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// lands between the two cannot make the timestamp go backwards. See the
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// AT91 version for why that matters.
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uint16_t cv_before = (uint16_t)tmr_counter_value_get(AT32_TMR_TIMESTAMP);
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bool overflowed = tmr_flag_get(AT32_TMR_TIMESTAMP, TMR_OVF_FLAG);
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uint16_t cv_after = (uint16_t)tmr_counter_value_get(AT32_TMR_TIMESTAMP);
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if (overflowed) {
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tmr_flag_clear(AT32_TMR_TIMESTAMP, TMR_OVF_FLAG);
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timestamp_high++;
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cv_before = cv_after;
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}
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return (((uint32_t)timestamp_high << 16) + cv_before) / TICKS_PER_CARRIER_PERIOD;
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}
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#endif // #ifndef AS_BOOTROM
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/**
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* Configure the timer to count up at the specified frequency.
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* @param frequency the frequency of timer running.
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*/
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static void configCounter(const uint32_t frequency) {
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crm_periph_clock_enable(AT32_CRM_TMR_PERIPH_32B_TIMER_CLK, TRUE);
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// AT32 has a 32-bit timer, perhaps we can achieve higher counting time without connecting the timer?
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tmr_32_bit_function_enable(AT32_TMR_32B_TIMER, TRUE);
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// TODO DXL 注意，如果apb1的预分频系数不是1，那么TIMER5的时钟速度会是apb1的两倍，这里记录下来，后期开发可能会遇到，如果完成移植，可将此段注释删除
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// See at32f435 manual reference 4.1.3
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// The timer uses APB1/2 as the clock. In particular, when the APB pre division coefficient is 1,
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// the clock frequency of the timer is equal to the clock frequency of APB1/2;
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// When the APB prescaler coefficient is not 1, the clock frequency of the timer is equal to twice the APB1/2 clock frequency.
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// So, if we are using not apb from ahb/1, must to div2.
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#define FREQUENCY_APB1 144000000UL // apb1 = ahb/2 = 144mhz, apb1*2 = TIMER_CLK, TIMER_CLK/192(divX) = 1.5mhz
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const uint32_t divX = (FREQUENCY_APB1 / frequency) * 2 - 1;
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tmr_base_init(AT32_TMR_32B_TIMER, UINT32_MAX - 1, divX);
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|
|
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tmr_cnt_dir_set(AT32_TMR_32B_TIMER, TMR_COUNT_UP);
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tmr_counter_enable(AT32_TMR_32B_TIMER, TRUE);
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}
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|
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// -------------------------------------------------------------------------
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|
// microseconds timer
|
|
// 1us = 1tick
|
|
// -------------------------------------------------------------------------
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|
|
|
void StartCountUS(void) {
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|
// see: https://github.com/RfidResearchGroup/proxmark3/blob/master/doc/clocks.md#occasional-tc0tc1--countus-functions
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configCounter(1000000); // 1 MHZ
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|
}
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|
|
|
uint32_t RAMFUNC GetCountUS(void) {
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|
// TODO DXL maybe no function call is a good idea?
|
|
// If it affects accuracy, you can consider directly reading the register.
|
|
// return AT32_TMR_32B_TIMER->cval;
|
|
return tmr_counter_value_get(AT32_TMR_32B_TIMER);
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|
}
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|
|
|
// -------------------------------------------------------------------------
|
|
// Timer for bitbanging, or LF stuff when you need a very precise timer
|
|
// 1us = 1.5ticks
|
|
// -------------------------------------------------------------------------
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|
|
|
void StartTicks(void) {
|
|
// see: https://github.com/RfidResearchGroup/proxmark3/blob/master/doc/clocks.md#occasional-tc0tc1--ticks-functions
|
|
configCounter(1500000); // 1.5 MHz
|
|
}
|
|
|
|
// Reset the count value to 0
|
|
void ResetTicks(void) {
|
|
tmr_counter_value_set(AT32_TMR_32B_TIMER, 0);
|
|
}
|
|
|
|
void StopTicks(void) {
|
|
tmr_counter_enable(AT32_TMR_32B_TIMER, FALSE);
|
|
crm_periph_clock_enable(AT32_CRM_TMR_PERIPH_32B_TIMER_CLK, FALSE);
|
|
// TODO DXL 也许需要在这里停止 其他定时器，因为PM3原本的代码有这个设计，但是我们需要查一下用处，看看是否能这么做
|
|
}
|
|
|
|
uint32_t GetTicks(void) {
|
|
// TODO DXL maybe no function call is a good idea?
|
|
// If it affects accuracy, you can consider directly reading the register.
|
|
// return AT32_TMR_32B_TIMER->cval;
|
|
return tmr_counter_value_get(AT32_TMR_32B_TIMER);
|
|
}
|