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153 Commits
Author SHA1 Message Date
iceman1001 2d610b8dc0 text & style 2025-06-08 10:02:00 +02:00
n-hutton 990e7b5e1f add bitfiles for prox ultimate build 2025-06-08 06:26:33 +01:00
n-hutton 3ef1486e79 change seed, making new iclass builds work again 2025-06-04 22:03:56 +01:00
Antiklesys a04fa57f86 Fpga images from orca release 
Fpga images from orca
 2025-06-03 18:09:22 +08:00
n-hutton 0871dfe99a revert date/time strip because of possible error with blue ice release 2025-06-02 19:25:49 +01:00
iceman1001 72a9f0a0a8 code style 2025-02-21 16:33:40 +01:00
n-hutton 982bef6705 fix build failure on linux machines with fwd decl 2025-02-20 15:55:43 +00:00
n-hutton 280b3301ee PR feedback and make things work generally 2025-02-20 14:51:08 +00:00
n-hutton e3b2bc9839 strip date time files 2025-02-20 14:39:31 +00:00
n-hutton bb4e14bb4c remove comment before PR open 2025-02-07 16:36:01 +00:00
n-hutton 6465f247ea force bitfiles to be identical for same source code 2025-02-07 16:27:08 +00:00
libin-kaandGitHub 537a9f0171 Add files via upload 
Add Proxmark3 Ultimate  FPGA   xc2s50-5-tq144.ucf  files

Signed-off-by: libin-ka <46210417+libin-ka@users.noreply.github.com>
 2024-12-03 21:04:50 +08:00
douniwan5788 9dd5b66c0a fix: FPGA config for ICOPYX 2024-08-26 20:56:36 +08:00
iceman1001 b50d921be3 own compiled 2024-02-03 16:11:00 +01:00
Christian Zietz 225bb420c6 Shorten threshold registers to number of used bits 2024-02-03 12:09:02 +01:00
Christian Zietz dbfd8b7a6d Make detection threshold for ISO14443A configurable 
This adds a new command "hw sethfthresh" to configure the thresholds
used inside the FPGA while demodulating ISO14443A. The thresholds
need to be increased on particularly noisy hardware, such as certain
Chinese PM3 Easy clones.
 2024-02-02 20:51:05 +01:00
iceman1001 e4835e69a3 recompiled the fpga images 2024-01-24 17:06:41 +01:00
Yann GASCUEL c27cf92b76 iso15sniff: enable lowsignal sniffing 2024-01-24 13:59:12 +01:00
Yann GASCUEL fa3c2e386b improve iso15 sniff quality 2024-01-24 13:59:12 +01:00
iceman1001 0c4a1066c1 text 2024-01-05 19:27:38 +01:00
Philippe Teuwen d74e264250 style 2023-09-07 20:13:18 +02:00
iceman1001 85aac72855 new fpga images 2023-08-29 16:46:52 +02:00
Alex 762c942e95 Redundant check 
A 3 bit counter will naturally roll over to zero on overflow, there is no need to explicitly check for max value and manually reset to zero
 2023-08-29 11:26:43 +02:00
Alex 61765cc933 More compact notation 2023-08-29 11:24:56 +02:00
iceman1001 ba320f26f7 ensure registers and vars is set correct 2023-08-28 15:34:36 +02:00