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This commit is contained in:
iceman1001
2026-08-29 17:42:29 +02:00
parent a0a3eb4bbf
commit 35c098d489
197 changed files with 30157 additions and 35538 deletions
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armlib/at32_i2c/at32f435_437_i2c_app.c
+229 -459
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File diff suppressed because it is too large Load Diff
armlib/at32_i2c/at32f435_437_i2c_app.h
+4 -8
View File
@@ -56,8 +56,7 @@ extern "C" {
* @{
*/
typedef enum
{
typedef enum {
I2C_MEM_ADDR_WIDIH_8 = 0x01, /*!< memory address is 8 bit */
I2C_MEM_ADDR_WIDIH_16 = 0x02, /*!< memory address is 16 bit */
} i2c_mem_address_width_type;
@@ -70,8 +69,7 @@ typedef enum
* @{
*/
typedef enum
{
typedef enum {
I2C_INT_MA_TX = 0,
I2C_INT_MA_RX,
I2C_INT_SLA_TX,
@@ -90,8 +88,7 @@ typedef enum
* @{
*/
typedef enum
{
typedef enum {
I2C_OK = 0, /*!< no error */
I2C_ERR_STEP_1, /*!< step 1 error */
I2C_ERR_STEP_2, /*!< step 2 error */
@@ -122,8 +119,7 @@ typedef enum
* @{
*/
typedef struct
{
typedef struct {
i2c_type *i2cx; /*!< i2c registers base address */
uint8_t *pbuff; /*!< pointer to i2c transfer buffer */
__IO uint16_t psize; /*!< i2c transfer size */
armlib/at32_sys/cmsis/cm4/core_support/arm_helium_utils.h
+33 -66
View File
@@ -53,8 +53,7 @@ Definitions available for MVEF only
***************************************/
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE)
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
{
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) {
float32_t acc;
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
@@ -94,8 +93,7 @@ Definitions available for f16 datatype with HW acceleration only
#if defined(ARM_FLOAT16_SUPPORTED)
#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
{
__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in) {
float16x8_t tmpVec;
_Float16 acc;
@@ -109,8 +107,7 @@ __STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
}
__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
float16x8_t vecIn)
{
float16x8_t vecIn) {
float16x8_t vecTmp, vecOut;
uint32_t tmp;
@@ -151,8 +148,7 @@ __STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(
float16x8_t vecIn,
float16_t *pOut)
{
float16_t *pOut) {
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn);
/*
* Cmplx sum is in 4rd & 5th f16 elt
@@ -190,8 +186,7 @@ Definitions available for MVEI and MVEF only
/* Following functions are used to transpose matrix in f32 and q31 cases */
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
uint32_t *pDataSrc,
uint32_t * pDataDest)
{
uint32_t *pDataDest) {
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
/*
*
@@ -207,8 +202,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
uint32_t *pDataSrc,
uint32_t * pDataDest)
{
uint32_t *pDataDest) {
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
/*
@@ -229,8 +223,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
return (ARM_MATH_SUCCESS);
}
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
{
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t *pDataSrc, uint32_t *pDataDest) {
/*
* 4x4 Matrix transposition
* is 4 x de-interleave operation
@@ -260,8 +253,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
uint16_t srcRows,
uint16_t srcCols,
uint32_t *pDataSrc,
uint32_t * pDataDest)
{
uint32_t *pDataDest) {
uint32x4_t vecOffs;
uint32_t i;
uint32_t blkCnt;
@@ -273,14 +265,12 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
vecOffs = vecOffs * srcCols;
i = srcCols;
do
{
do {
pDataC = (uint32_t const *) pDataSrc;
pDataDestR = pDataDest;
blkCnt = srcRows >> 2;
while (blkCnt > 0U)
{
while (blkCnt > 0U) {
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
vstrwq(pDataDestR, vecIn);
pDataDestR += 4;
@@ -295,8 +285,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
* tail
*/
blkCnt = srcRows & 3;
if (blkCnt > 0U)
{
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp32q(blkCnt);
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
vstrwq_p(pDataDestR, vecIn, p0);
@@ -304,8 +293,7 @@ __STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
pDataSrc += 1;
pDataDest += srcRows;
}
while (--i);
} while (--i);
return (ARM_MATH_SUCCESS);
}
@@ -316,8 +304,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
uint32_t *pDataSrc,
uint16_t dstRows,
uint16_t dstCols,
uint32_t *pDataDest)
{
uint32_t *pDataDest) {
uint32_t i;
uint32_t const *pDataC;
uint32_t *pDataRow;
@@ -330,8 +317,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
/*
* Check for matrix mismatch condition
*/
if ((srcRows != dstCols) || (srcCols != dstRows))
{
if ((srcRows != dstCols) || (srcCols != dstRows)) {
/*
* Set status as ARM_MATH_SIZE_MISMATCH
*/
@@ -352,15 +338,13 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
pDataRow = pDataSrc;
pDataDestRow = pDataDest;
i = srcCols;
do
{
do {
pDataC = (uint32_t const *) pDataRow;
pDataDestR = pDataDestRow;
vecOffsCur = vecOffsRef;
blkCnt = (srcRows * CMPLX_DIM) >> 2;
while (blkCnt > 0U)
{
while (blkCnt > 0U) {
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
vstrwq(pDataDestR, vecIn);
pDataDestR += 4;
@@ -375,8 +359,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
* (will be merged thru tail predication)
*/
blkCnt = (srcRows * CMPLX_DIM) & 3;
if (blkCnt > 0U)
{
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp32q(blkCnt);
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
vstrwq_p(pDataDestR, vecIn, p0);
@@ -384,14 +367,12 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
pDataRow += CMPLX_DIM;
pDataDestRow += (srcRows * CMPLX_DIM);
}
while (--i);
} while (--i);
return (ARM_MATH_SUCCESS);
}
__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest)
{
__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t *pDataSrc, uint16_t *pDataDest) {
pDataDest[0] = pDataSrc[0];
pDataDest[3] = pDataSrc[3];
pDataDest[2] = pDataSrc[1];
@@ -400,8 +381,7 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t
return (ARM_MATH_SUCCESS);
}
__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
{
__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t *pDataSrc, uint16_t *pDataDest) {
static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 };
uint16x8_t vecOffs1;
uint16x8_t vecIn1;
@@ -423,8 +403,7 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint
}
__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
{
__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t *pDataSrc, uint16_t *pDataDest) {
static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 };
static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 };
uint16x8_t vecOffs1, vecOffs2;
@@ -459,8 +438,7 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
uint16_t srcRows,
uint16_t srcCols,
uint16_t *pDataSrc,
uint16_t * pDataDest)
{
uint16_t *pDataDest) {
uint16x8_t vecOffs;
uint32_t i;
uint32_t blkCnt;
@@ -472,14 +450,12 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
vecOffs = vecOffs * srcCols;
i = srcCols;
while(i > 0U)
{
while (i > 0U) {
pDataC = (uint16_t const *) pDataSrc;
pDataDestR = pDataDest;
blkCnt = srcRows >> 3;
while (blkCnt > 0U)
{
while (blkCnt > 0U) {
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
vstrhq_u16(pDataDestR, vecIn);
pDataDestR += 8;
@@ -494,8 +470,7 @@ __STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
* tail
*/
blkCnt = srcRows & 7;
if (blkCnt > 0U)
{
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp16q(blkCnt);
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
vstrhq_p_u16(pDataDestR, vecIn, p0);
@@ -515,8 +490,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
uint16_t *pDataSrc,
uint16_t dstRows,
uint16_t dstCols,
uint16_t *pDataDest)
{
uint16_t *pDataDest) {
static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
int i;
uint16x8_t vecOffsRef, vecOffsCur;
@@ -530,8 +504,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
/*
* Check for matrix mismatch condition
*/
if ((srcRows != dstCols) || (srcCols != dstRows))
{
if ((srcRows != dstCols) || (srcCols != dstRows)) {
/*
* Set status as ARM_MATH_SIZE_MISMATCH
*/
@@ -557,15 +530,13 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
pDataRow = pDataSrc;
pDataDestRow = pDataDest;
i = srcCols;
do
{
do {
pDataC = (uint16_t const *) pDataRow;
pDataDestR = pDataDestRow;
vecOffsCur = vecOffsRef;
blkCnt = (srcRows * CMPLX_DIM) >> 3;
while (blkCnt > 0U)
{
while (blkCnt > 0U) {
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
vstrhq(pDataDestR, vecIn);
pDataDestR += 8; // VEC_LANES_U16
@@ -580,8 +551,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
* (will be merged thru tail predication)
*/
blkCnt = (srcRows * CMPLX_DIM) & 0x7;
if (blkCnt > 0U)
{
if (blkCnt > 0U) {
mve_pred16_t p0 = vctp16q(blkCnt);
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
vstrhq_p(pDataDestR, vecIn, p0);
@@ -589,8 +559,7 @@ __STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
pDataRow += CMPLX_DIM;
pDataDestRow += (srcRows * CMPLX_DIM);
}
while (--i);
} while (--i);
return (ARM_MATH_SUCCESS);
}
@@ -610,8 +579,7 @@ Definitions available for MVEI only
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
{
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) {
q63x2_t vecTmpLL;
q31x4_t vecTmp0, vecTmp1;
q31_t scale;
@@ -678,8 +646,7 @@ __STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
#endif
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
{
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) {
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
q15x8_t vecTmp0, vecTmp1;
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
armlib/at32_sys/cmsis/cm4/core_support/arm_math_memory.h
+5 -10
View File
@@ -74,8 +74,7 @@ extern "C"
@return Q31 value
*/
__STATIC_FORCEINLINE q31_t read_q15x2(
q15_t const * pQ15)
{
q15_t const *pQ15) {
q31_t val;
#ifdef __ARM_FEATURE_UNALIGNED
@@ -109,8 +108,7 @@ __STATIC_FORCEINLINE q31_t read_q15x2 (
*/
__STATIC_FORCEINLINE void write_q15x2_ia(
q15_t **pQ15,
q31_t value)
{
q31_t value) {
q31_t val = value;
#ifdef __ARM_FEATURE_UNALIGNED
memcpy(*pQ15, &val, 4);
@@ -130,8 +128,7 @@ __STATIC_FORCEINLINE void write_q15x2_ia (
*/
__STATIC_FORCEINLINE void write_q15x2(
q15_t *pQ15,
q31_t value)
{
q31_t value) {
q31_t val = value;
#ifdef __ARM_FEATURE_UNALIGNED
@@ -149,8 +146,7 @@ __STATIC_FORCEINLINE void write_q15x2 (
@return Q31 value
*/
__STATIC_FORCEINLINE q31_t read_q7x4(
q7_t const * pQ7)
{
q7_t const *pQ7) {
q31_t val;
#ifdef __ARM_FEATURE_UNALIGNED
@@ -183,8 +179,7 @@ __STATIC_FORCEINLINE q31_t read_q7x4 (
*/
__STATIC_FORCEINLINE void write_q7x4_ia(
q7_t **pQ7,
q31_t value)
{
q31_t value) {
q31_t val = value;
#ifdef __ARM_FEATURE_UNALIGNED
memcpy(*pQ7, &val, 4);
armlib/at32_sys/cmsis/cm4/core_support/arm_math_types.h
+3 -6
View File
@@ -414,8 +414,7 @@ extern "C"
/**
* @brief 32-bit ubiquitous 128-bit vector data type
*/
typedef union _any32x4_t
{
typedef union _any32x4_t {
float32x4_t f;
int32x4_t i;
} any32x4_t;
@@ -528,8 +527,7 @@ extern "C"
/**
* @brief 32-bit ubiquitous 64-bit vector data type
*/
typedef union _any32x2_t
{
typedef union _any32x2_t {
float32x2_t f;
int32x2_t i;
} any32x2_t;
@@ -596,8 +594,7 @@ extern "C"
* @brief Error status returned by some functions in the library.
*/
typedef enum
{
typedef enum {
ARM_MATH_SUCCESS = 0, /**< No error */
ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
armlib/at32_sys/cmsis/cm4/core_support/arm_math_types_f16.h
+2 -4
View File
@@ -83,8 +83,7 @@ won't be built.
/**
* @brief 16-bit ubiquitous 128-bit vector data type
*/
typedef union _any16x8_t
{
typedef union _any16x8_t {
float16x8_t f;
int16x8_t i;
} any16x8_t;
@@ -124,8 +123,7 @@ won't be built.
/**
* @brief 16-bit ubiquitous 64-bit vector data type
*/
typedef union _any16x4_t
{
typedef union _any16x4_t {
float16x4_t f;
int16x4_t i;
} any16x4_t;
armlib/at32_sys/cmsis/cm4/core_support/arm_vec_math.h
+16 -32
View File
@@ -44,8 +44,7 @@ static const float32_t __logf_rng_f32=0.693147180f;
/* fast inverse approximation (3x newton) */
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
f32x4_t x)
{
f32x4_t x) {
q31x4_t m;
f32x4_t b;
any32x4_t xinv;
@@ -77,8 +76,7 @@ __STATIC_INLINE f32x4_t vrecip_medprec_f32(
/* fast inverse approximation (4x newton) */
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
f32x4_t x)
{
f32x4_t x) {
q31x4_t m;
f32x4_t b;
any32x4_t xinv;
@@ -113,8 +111,7 @@ __STATIC_INLINE f32x4_t vrecip_hiprec_f32(
}
__STATIC_INLINE f32x4_t vdiv_f32(
f32x4_t num, f32x4_t den)
{
f32x4_t num, f32x4_t den) {
return vmulq(num, vrecip_hiprec_f32(den));
}
@@ -127,8 +124,7 @@ __STATIC_INLINE f32x4_t vdiv_f32(
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
f32x4_t x,
const float32_t * coeffs)
{
const float32_t *coeffs) {
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
@@ -142,8 +138,7 @@ __STATIC_INLINE f32x4_t vtaylor_polyq_f32(
__STATIC_INLINE f32x4_t vmant_exp_f32(
f32x4_t x,
int32x4_t * e)
{
int32x4_t *e) {
any32x4_t r;
int32x4_t n;
@@ -157,8 +152,7 @@ __STATIC_INLINE f32x4_t vmant_exp_f32(
}
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
{
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) {
q31x4_t vecExpUnBiased;
f32x4_t vecTmpFlt0, vecTmpFlt1;
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
@@ -218,8 +212,7 @@ __STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
}
__STATIC_INLINE f32x4_t vexpq_f32(
f32x4_t x)
{
f32x4_t x) {
// Perform range reduction [-log(2),log(2)]
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
@@ -234,8 +227,7 @@ __STATIC_INLINE f32x4_t vexpq_f32(
return poly;
}
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
{
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) {
f32x4_t r = x;
nb--;
while (nb > 0) {
@@ -245,8 +237,7 @@ __STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
return (r);
}
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
{
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) {
f32x4_t vecSx, vecW, vecTmp;
any32x4_t v;
@@ -276,8 +267,7 @@ __STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
}
__STATIC_INLINE f32x4_t vtanhq_f32(
f32x4_t val)
{
f32x4_t val) {
f32x4_t x =
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
@@ -289,8 +279,7 @@ __STATIC_INLINE f32x4_t vtanhq_f32(
__STATIC_INLINE f32x4_t vpowq_f32(
f32x4_t val,
f32x4_t n)
{
f32x4_t n) {
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
}
@@ -309,12 +298,10 @@ __STATIC_INLINE f32x4_t vpowq_f32(
* @return x^nb
*
*/
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
{
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) {
float32x4_t r = x;
nb --;
while(nb > 0)
{
while (nb > 0) {
r = vmulq_f32(r, x);
nb--;
}
@@ -322,8 +309,7 @@ __STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
}
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
{
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) {
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
float32x4_t e = vrsqrteq_f32(x1);
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
@@ -331,8 +317,7 @@ __STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
return vmulq_f32(x, e);
}
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
{
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) {
float32x4_t tempF;
int32x4_t tempHI, tempLO;
@@ -349,8 +334,7 @@ __STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
return (vcombine_s16(vqmovn_s32(tempLO), vqmovn_s32(tempHI)));
}
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
{
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) {
float32x4_t temp;
temp = vcvtq_n_f32_s32(vec, 31);
armlib/at32_sys/cmsis/cm4/core_support/arm_vec_math_f16.h
+10 -20
View File
@@ -45,8 +45,7 @@ static const float16_t __logf_rng_f16=0.693147180f16;
/* fast inverse approximation (3x newton) */
__STATIC_INLINE f16x8_t vrecip_medprec_f16(
f16x8_t x)
{
f16x8_t x) {
q15x8_t m;
f16x8_t b;
any16x8_t xinv;
@@ -79,8 +78,7 @@ __STATIC_INLINE f16x8_t vrecip_medprec_f16(
/* fast inverse approximation (4x newton) */
__STATIC_INLINE f16x8_t vrecip_hiprec_f16(
f16x8_t x)
{
f16x8_t x) {
q15x8_t m;
f16x8_t b;
any16x8_t xinv;
@@ -115,8 +113,7 @@ __STATIC_INLINE f16x8_t vrecip_hiprec_f16(
}
__STATIC_INLINE f16x8_t vdiv_f16(
f16x8_t num, f16x8_t den)
{
f16x8_t num, f16x8_t den) {
return vmulq(num, vrecip_hiprec_f16(den));
}
@@ -130,8 +127,7 @@ __STATIC_INLINE f16x8_t vdiv_f16(
__STATIC_INLINE float16x8_t vtaylor_polyq_f16(
float16x8_t x,
const float16_t * coeffs)
{
const float16_t *coeffs) {
float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]);
float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]);
float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]);
@@ -155,8 +151,7 @@ __STATIC_INLINE float16x8_t vtaylor_polyq_f16(
vecExpUnBiased = n; \
vecTmpFlt1 = r.f;
__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn)
{
__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn) {
q15x8_t vecExpUnBiased;
float16x8_t vecTmpFlt0, vecTmpFlt1;
float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
@@ -216,8 +211,7 @@ __STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn)
}
__STATIC_INLINE float16x8_t vexpq_f16(
float16x8_t x)
{
float16x8_t x) {
// Perform range reduction [-log(2),log(2)]
int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16));
float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16));
@@ -232,8 +226,7 @@ __STATIC_INLINE float16x8_t vexpq_f16(
return poly;
}
__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb)
{
__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb) {
float16x8_t r = x;
nb--;
while (nb > 0) {
@@ -245,15 +238,13 @@ __STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb)
__STATIC_INLINE f16x8_t vpowq_f16(
f16x8_t val,
f16x8_t n)
{
f16x8_t n) {
return vexpq_f16(vmulq_f16(n, vlogq_f16(val)));
}
#define INV_NEWTON_INIT_F16 0x7773
__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn)
{
__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn) {
f16x8_t vecSx, vecW, vecTmp;
any16x8_t v;
@@ -283,8 +274,7 @@ __STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn)
}
__STATIC_INLINE f16x8_t vtanhq_f16(
f16x8_t val)
{
f16x8_t val) {
f16x8_t x =
vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16));
f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16));
armlib/at32_sys/cmsis/cm4/core_support/cmsis_armcc.h
+31 -64
View File
@@ -205,8 +205,7 @@
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) {
rev16 r0, r0
bx lr
}
@@ -220,8 +219,7 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) {
revsh r0, r0
bx lr
}
@@ -258,14 +256,12 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) {
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
for (value >>= 1U; value != 0U; value >>= 1U) {
result <<= 1U;
result |= value & 1U;
s--;
@@ -407,8 +403,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) {
rrx r0, r0
bx lr
}
@@ -478,18 +473,13 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
if ((sat >= 1U) && (sat <= 32U)) {
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
if (val > max) {
return max;
}
else if (val < min)
{
} else if (val < min) {
return min;
}
}
@@ -503,17 +493,12 @@ __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint3
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
if (sat <= 31U) {
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
if (val > (int32_t)max) {
return max;
}
else if (val < 0)
{
} else if (val < 0) {
return 0U;
}
}
@@ -552,8 +537,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
__STATIC_INLINE uint32_t __get_CONTROL(void) {
register uint32_t __regControl __ASM("control");
return (__regControl);
}
@@ -564,8 +548,7 @@ __STATIC_INLINE uint32_t __get_CONTROL(void)
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__STATIC_INLINE void __set_CONTROL(uint32_t control) {
register uint32_t __regControl __ASM("control");
__regControl = control;
__ISB();
@@ -577,8 +560,7 @@ __STATIC_INLINE void __set_CONTROL(uint32_t control)
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
__STATIC_INLINE uint32_t __get_IPSR(void) {
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
@@ -589,8 +571,7 @@ __STATIC_INLINE uint32_t __get_IPSR(void)
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
__STATIC_INLINE uint32_t __get_APSR(void) {
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
@@ -601,8 +582,7 @@ __STATIC_INLINE uint32_t __get_APSR(void)
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
__STATIC_INLINE uint32_t __get_xPSR(void) {
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
@@ -613,8 +593,7 @@ __STATIC_INLINE uint32_t __get_xPSR(void)
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
__STATIC_INLINE uint32_t __get_PSP(void) {
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
@@ -625,8 +604,7 @@ __STATIC_INLINE uint32_t __get_PSP(void)
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) {
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
@@ -637,8 +615,7 @@ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
__STATIC_INLINE uint32_t __get_MSP(void) {
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
@@ -649,8 +626,7 @@ __STATIC_INLINE uint32_t __get_MSP(void)
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) {
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
@@ -661,8 +637,7 @@ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
__STATIC_INLINE uint32_t __get_PRIMASK(void) {
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
@@ -673,8 +648,7 @@ __STATIC_INLINE uint32_t __get_PRIMASK(void)
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) {
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
@@ -704,8 +678,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
__STATIC_INLINE uint32_t __get_BASEPRI(void) {
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
@@ -716,8 +689,7 @@ __STATIC_INLINE uint32_t __get_BASEPRI(void)
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) {
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
@@ -729,8 +701,7 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) {
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
@@ -741,8 +712,7 @@ __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
__STATIC_INLINE uint32_t __get_FAULTMASK(void) {
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
@@ -753,8 +723,7 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) {
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
@@ -768,8 +737,7 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
__STATIC_INLINE uint32_t __get_FPSCR(void) {
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
@@ -785,8 +753,7 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) {
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
armlib/at32_sys/cmsis/cm4/core_support/cmsis_armclang.h
+68 -138
View File
File diff suppressed because it is too large Load Diff
armlib/at32_sys/cmsis/cm4/core_support/cmsis_armclang_ltm.h
+125 -252
View File
File diff suppressed because it is too large Load Diff
armlib/at32_sys/cmsis/cm4/core_support/cmsis_gcc.h
+151 -304
View File
File diff suppressed because it is too large Load Diff
armlib/at32_sys/cmsis/cm4/core_support/cmsis_iccarm.h
+65 -132
View File
@@ -180,8 +180,7 @@
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
__IAR_FT uint16_t __iar_uint16_read(void const *ptr) {
return *(__packed uint16_t *)(ptr);
}
#pragma language=restore
@@ -192,8 +191,7 @@ __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) {
*(__packed uint16_t *)(ptr) = val;;
}
#pragma language=restore
@@ -203,8 +201,7 @@ __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
__IAR_FT uint32_t __iar_uint32_read(void const *ptr) {
return *(__packed uint32_t *)(ptr);
}
#pragma language=restore
@@ -214,8 +211,7 @@ __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) {
*(__packed uint32_t *)(ptr) = val;;
}
#pragma language=restore
@@ -356,8 +352,7 @@ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) {
__arm_wsr("CONTROL", control);
__iar_builtin_ISB();
}
@@ -384,8 +379,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) {
__arm_wsr("CONTROL_NS", control);
__iar_builtin_ISB();
}
@@ -433,8 +427,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
__IAR_FT int16_t __REVSH(int16_t val) {
return (int16_t) __iar_builtin_REVSH(val);
}
@@ -555,27 +548,23 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
__STATIC_INLINE uint8_t __CLZ(uint32_t data) {
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
while ((data & mask) == 0U) {
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
__STATIC_INLINE uint32_t __RBIT(uint32_t v) {
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
for (v >>= 1U; v; v >>= 1U) {
r <<= 1U;
r |= v & 1U;
sc--;
@@ -583,8 +572,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
__STATIC_INLINE uint32_t __get_APSR(void) {
uint32_t res;
__asm("MRS %0,APSR" : "=r"(res));
return res;
@@ -611,13 +599,11 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) {
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) {
return __STREX(value, (unsigned long *)ptr);
}
#endif
@@ -626,15 +612,13 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
__IAR_FT uint32_t __RRX(uint32_t value) {
uint32_t result;
__ASM volatile("RRX %0, %1" : "=r"(result) : "r"(value));
return (result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__IAR_FT void __set_BASEPRI_MAX(uint32_t value) {
__asm volatile("MSR BASEPRI_MAX,%0"::"r"(value));
}
@@ -645,16 +629,14 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) {
return (op1 >> op2) | (op1 << ((sizeof(op1) * 8) - op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
__IAR_FT uint32_t __get_MSPLIM(void) {
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
@@ -666,8 +648,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
__IAR_FT void __set_MSPLIM(uint32_t value) {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
@@ -677,8 +658,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
__IAR_FT uint32_t __get_PSPLIM(void) {
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
@@ -690,8 +670,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
__IAR_FT void __set_PSPLIM(uint32_t value) {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
@@ -701,92 +680,77 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void) {
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) {
__asm volatile("MSR CONTROL_NS,%0" :: "r"(value));
__iar_builtin_ISB();
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
__IAR_FT uint32_t __TZ_get_PSP_NS(void) {
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__IAR_FT void __TZ_set_PSP_NS(uint32_t value) {
__asm volatile("MSR PSP_NS,%0" :: "r"(value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
__IAR_FT uint32_t __TZ_get_MSP_NS(void) {
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__IAR_FT void __TZ_set_MSP_NS(uint32_t value) {
__asm volatile("MSR MSP_NS,%0" :: "r"(value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
__IAR_FT uint32_t __TZ_get_SP_NS(void) {
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__IAR_FT void __TZ_set_SP_NS(uint32_t value) {
__asm volatile("MSR SP_NS,%0" :: "r"(value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) {
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) {
__asm volatile("MSR PRIMASK_NS,%0" :: "r"(value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) {
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) {
__asm volatile("MSR BASEPRI_NS,%0" :: "r"(value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) {
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) {
__asm volatile("MSR FAULTMASK_NS,%0" :: "r"(value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) {
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
@@ -798,8 +762,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) {
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
@@ -809,15 +772,13 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) {
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r"(res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) {
__asm volatile("MSR MSPLIM_NS,%0" :: "r"(value));
}
@@ -828,35 +789,25 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) {
if ((sat >= 1U) && (sat <= 32U)) {
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
if (val > max) {
return max;
}
else if (val < min)
{
} else if (val < min) {
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) {
if (sat <= 31U) {
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
if (val > (int32_t)max) {
return max;
}
else if (val < 0)
{
} else if (val < 0) {
return 0U;
}
}
@@ -866,39 +817,33 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) {
uint32_t res;
__ASM volatile("LDRBT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) {
uint32_t res;
__ASM volatile("LDRHT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr) {
uint32_t res;
__ASM volatile("LDRT %0, [%1]" : "=r"(res) : "r"(addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) {
__ASM volatile("STRBT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) {
__ASM volatile("STRHT %1, [%0]" : : "r"(addr), "r"((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) {
__ASM volatile("STRT %1, [%0]" : : "r"(addr), "r"(value) : "memory");
}
@@ -908,79 +853,67 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) {
uint32_t res;
__ASM volatile("LDAB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) {
uint32_t res;
__ASM volatile("LDAH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr) {
uint32_t res;
__ASM volatile("LDA %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) {
__ASM volatile("STLB %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) {
__ASM volatile("STLH %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) {
__ASM volatile("STL %1, [%0]" :: "r"(ptr), "r"(value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) {
uint32_t res;
__ASM volatile("LDAEXB %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) {
uint32_t res;
__ASM volatile("LDAEXH %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) {
uint32_t res;
__ASM volatile("LDAEX %0, [%1]" : "=r"(res) : "r"(ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) {
uint32_t res;
__ASM volatile("STLEXB %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) {
uint32_t res;
__ASM volatile("STLEXH %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) {
uint32_t res;
__ASM volatile("STLEX %0, %2, [%1]" : "=r"(res) : "r"(ptr), "r"(value) : "memory");
return res;
armlib/at32_sys/cmsis/cm4/core_support/core_cm4.h
+63 -133
View File
@@ -261,10 +261,8 @@
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
@@ -300,10 +298,8 @@ typedef union
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
@@ -318,10 +314,8 @@ typedef union
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0: 1; /*!< bit: 9 Reserved */
uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */
@@ -373,10 +367,8 @@ typedef union
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
typedef union {
struct {
uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
@@ -408,8 +400,7 @@ typedef union
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
typedef struct {
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
@@ -442,8 +433,7 @@ typedef struct
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
typedef struct {
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
@@ -721,8 +711,7 @@ typedef struct
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
typedef struct {
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
@@ -761,8 +750,7 @@ typedef struct
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
@@ -813,10 +801,8 @@ typedef struct
/**
\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__OM union
{
typedef struct {
__OM union {
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
@@ -901,8 +887,7 @@ typedef struct
/**
\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
*/
typedef struct
{
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
__IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
__IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
@@ -1048,8 +1033,7 @@ typedef struct
/**
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct
{
typedef struct {
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
@@ -1210,8 +1194,7 @@ typedef struct
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
typedef struct {
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
@@ -1306,8 +1289,7 @@ typedef struct
/**
\brief Structure type to access the Floating Point Unit (FPU).
*/
typedef struct
{
typedef struct {
uint32_t RESERVED0[1U];
__IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
@@ -1418,8 +1400,7 @@ typedef struct
/**
\brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
typedef struct {
__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
@@ -1650,8 +1631,7 @@ typedef struct
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
@@ -1669,8 +1649,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) {
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1681,10 +1660,8 @@ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__COMPILER_BARRIER();
@@ -1700,14 +1677,10 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
@@ -1719,10 +1692,8 @@ __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
@@ -1738,14 +1709,10 @@ __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
@@ -1757,10 +1724,8 @@ __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
@@ -1772,10 +1737,8 @@ __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
@@ -1789,14 +1752,10 @@ __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 1 Interrupt status is active.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0) {
return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
} else {
return (0U);
}
}
@@ -1811,14 +1770,10 @@ __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) {
if ((int32_t)(IRQn) >= 0) {
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
else
{
} else {
SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
@@ -1833,15 +1788,11 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) {
if ((int32_t)(IRQn) >= 0)
{
if ((int32_t)(IRQn) >= 0) {
return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
}
else
{
} else {
return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) - 4UL] >> (8U - __NVIC_PRIO_BITS)));
}
}
@@ -1858,8 +1809,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) {
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@@ -1885,8 +1835,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority) {
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
@@ -1908,8 +1857,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
/* ARM Application Note 321 states that the M4 does not require the architectural barrier */
@@ -1924,8 +1872,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
@@ -1935,8 +1882,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) {
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
@@ -1944,8 +1890,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
for (;;) { /* wait until reset */
__NOP();
}
}
@@ -1978,17 +1923,13 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
__STATIC_INLINE uint32_t SCB_GetFPUType(void) {
uint32_t mvfr0;
mvfr0 = FPU->MVFR0;
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
{
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) {
return 1U; /* Single precision FPU */
}
else
{
} else {
return 0U; /* No FPU */
}
}
@@ -2019,10 +1960,8 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) {
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
return (1UL); /* Reload value impossible */
}
@@ -2061,13 +2000,10 @@ extern volatile int32_t ITM_RxBuffer; /*!< External
\param [in] ch Character to transmit.
\returns Character to transmit.
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) {
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0U].u32 == 0UL)
{
((ITM->TER & 1UL) != 0UL)) { /* ITM Port #0 enabled */
while (ITM->PORT[0U].u32 == 0UL) {
__NOP();
}
ITM->PORT[0U].u8 = (uint8_t)ch;
@@ -2082,12 +2018,10 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
\return Received character.
\return -1 No character pending.
*/
__STATIC_INLINE int32_t ITM_ReceiveChar (void)
{
__STATIC_INLINE int32_t ITM_ReceiveChar(void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
{
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
@@ -2102,15 +2036,11 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void)
\return 0 No character available.
\return 1 Character available.
*/
__STATIC_INLINE int32_t ITM_CheckChar (void)
{
__STATIC_INLINE int32_t ITM_CheckChar(void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
{
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
}
else
{
} else {
return (1); /* character available */
}
}
armlib/at32_sys/cmsis/cm4/core_support/mpu_armv7.h
+8 -16
View File
@@ -188,8 +188,7 @@ typedef struct {
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) {
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
@@ -201,8 +200,7 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__STATIC_INLINE void ARM_MPU_Disable(void) {
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
@@ -215,8 +213,7 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) {
MPU->RNR = rnr;
MPU->RASR = 0U;
}
@@ -225,8 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) {
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
@@ -236,8 +232,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
* \param rbar Value for RBAR register.
* \param rasr Value for RASR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) {
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
@@ -248,11 +243,9 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len) {
uint32_t i;
for (i = 0U; i < len; ++i)
{
for (i = 0U; i < len; ++i) {
dst[i] = src[i];
}
}
@@ -261,8 +254,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const *table, uint32_t cnt) {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U;
while (cnt > MPU_TYPE_RALIASES) {
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES * rowWordSize);
armlib/at32_sys/cmsis/cm4/core_support/mpu_armv8.h
+18 -36
View File
@@ -127,8 +127,7 @@ typedef struct {
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) {
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
@@ -140,8 +139,7 @@ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__STATIC_INLINE void ARM_MPU_Disable(void) {
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
@@ -155,8 +153,7 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) {
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
@@ -168,8 +165,7 @@ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__STATIC_INLINE void ARM_MPU_Disable_NS(void) {
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
@@ -185,8 +181,7 @@ __STATIC_INLINE void ARM_MPU_Disable_NS(void)
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type *mpu, uint8_t idx, uint8_t attr) {
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
@@ -202,8 +197,7 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) {
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
@@ -212,8 +206,7 @@ __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) {
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
@@ -222,8 +215,7 @@ __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type *mpu, uint32_t rnr) {
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
@@ -231,8 +223,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) {
ARM_MPU_ClrRegionEx(MPU, rnr);
}
@@ -240,8 +231,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) {
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
@@ -252,8 +242,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) {
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
@@ -264,8 +253,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) {
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
@@ -275,8 +263,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) {
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
@@ -286,11 +273,9 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len) {
uint32_t i;
for (i = 0U; i < len; ++i)
{
for (i = 0U; i < len; ++i) {
dst[i] = src[i];
}
}
@@ -301,8 +286,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt) {
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U;
if (cnt == 1U) {
mpu->RNR = rnr;
@@ -331,8 +315,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt) {
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
@@ -342,8 +325,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt) {
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
armlib/at32_sys/cmsis/cm4/core_support/pmu_armv8.h
+14 -28
View File
@@ -195,16 +195,14 @@ __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
/**
\brief Enable the PMU
*/
__STATIC_INLINE void ARM_PMU_Enable(void)
{
__STATIC_INLINE void ARM_PMU_Enable(void) {
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
}
/**
\brief Disable the PMU
*/
__STATIC_INLINE void ARM_PMU_Disable(void)
{
__STATIC_INLINE void ARM_PMU_Disable(void) {
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
}
@@ -213,24 +211,21 @@ __STATIC_INLINE void ARM_PMU_Disable(void)
\param [in] num Event counter (0-30) to configure
\param [in] type Event to count
*/
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
{
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) {
PMU->EVTYPER[num] = type;
}
/**
\brief Reset cycle counter
*/
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
{
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) {
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
}
/**
\brief Reset all event counters
*/
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
{
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) {
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
}
@@ -241,8 +236,7 @@ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
{
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) {
PMU->CNTENSET = mask;
}
@@ -253,8 +247,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
{
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) {
PMU->CNTENCLR = mask;
}
@@ -262,8 +255,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
\brief Read cycle counter
\return Cycle count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
{
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) {
return PMU->CCNTR;
}
@@ -272,8 +264,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
\param [in] num Event counter (0-30) to read
\return Event count
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
{
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) {
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
}
@@ -283,8 +274,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
{
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) {
return PMU->OVSSET;
}
@@ -295,8 +285,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
{
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) {
PMU->OVSCLR = mask;
}
@@ -307,8 +296,7 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
{
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) {
PMU->INTENSET = mask;
}
@@ -319,8 +307,7 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
- event counters (0-30)
- cycle counter
*/
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
{
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) {
PMU->INTENCLR = mask;
}
@@ -329,8 +316,7 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
\param [in] mask Counters to increment
\note Software increment bits for one or more event counters (0-30)
*/
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
{
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) {
PMU->SWINC = mask;
}
armlib/at32_sys/cmsis/cm4/device_support/at32f435_437.h
+1 -2
View File
@@ -225,8 +225,7 @@ extern "C" {
* @brief at32f435_437 interrupt number definition, according to the selected device
* in @ref library_configuration_section
*/
typedef enum IRQn
{
typedef enum IRQn {
/****** cortex-m4 processor exceptions numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
armlib/at32_sys/cmsis/cm4/device_support/system_at32f435_437.c
+5 -11
View File
@@ -60,8 +60,7 @@ unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequen
* @param none
* @retval none
*/
void SystemInit (void)
{
void SystemInit(void) {
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U * 2U) | /* set cp10 full access */
(3U << 11U * 2U)); /* set cp11 full access */
@@ -113,8 +112,7 @@ void SystemInit (void)
* @param none
* @retval none
*/
void system_core_clock_update(void)
{
void system_core_clock_update(void) {
uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
uint32_t temp = 0, div_value = 0;
crm_sclk_type sclk_source;
@@ -125,8 +123,7 @@ void system_core_clock_update(void)
/* get sclk source */
sclk_source = crm_sysclk_switch_status_get();
switch(sclk_source)
{
switch (sclk_source) {
case CRM_SCLK_HICK:
if (((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
system_core_clock = HICK_VALUE * 6;
@@ -145,13 +142,10 @@ void system_core_clock_update(void)
pll_ms = CRM->pllcfg_bit.pllms;
pll_fr = pll_fr_table[CRM->pllcfg_bit.pllfr];
if (pll_clock_source == CRM_PLL_SOURCE_HICK)
{
if (pll_clock_source == CRM_PLL_SOURCE_HICK) {
/* hick selected as pll clock entry */
pllrcsfreq = HICK_VALUE;
}
else
{
} else {
/* hext selected as pll clock entry */
pllrcsfreq = HEXT_VALUE;
}
armlib/at32_sys/drivers/inc/at32f435_437_acc.h
+13 -26
View File
@@ -69,17 +69,14 @@ extern "C" {
/**
* @brief type define acc register all
*/
typedef struct
{
typedef struct {
/**
* @brief acc sts register, offset:0x00
*/
union
{
union {
__IO uint32_t sts;
struct
{
struct {
__IO uint32_t calrdy : 1; /* [0] */
__IO uint32_t rslost : 1; /* [1] */
__IO uint32_t reserved1 : 30;/* [31:2] */
@@ -89,11 +86,9 @@ typedef struct
/**
* @brief acc ctrl1 register, offset:0x04
*/
union
{
union {
__IO uint32_t ctrl1;
struct
{
struct {
__IO uint32_t calon : 1; /* [0] */
__IO uint32_t entrim : 1; /* [1] */
__IO uint32_t reserved1 : 2; /* [3:2] */
@@ -108,11 +103,9 @@ typedef struct
/**
* @brief acc ctrl2 register, offset:0x08
*/
union
{
union {
__IO uint32_t ctrl2;
struct
{
struct {
__IO uint32_t hickcal : 8; /* [7:0] */
__IO uint32_t hicktrim : 6; /* [13:8] */
__IO uint32_t reserved1 : 18;/* [31:14] */
@@ -122,11 +115,9 @@ typedef struct
/**
* @brief acc acc_c1 register, offset:0x0C
*/
union
{
union {
__IO uint32_t c1;
struct
{
struct {
__IO uint32_t c1 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c1_bit;
@@ -135,11 +126,9 @@ typedef struct
/**
* @brief acc acc_c2 register, offset:0x10
*/
union
{
union {
__IO uint32_t c2;
struct
{
struct {
__IO uint32_t c2 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c2_bit;
@@ -148,11 +137,9 @@ typedef struct
/**
* @brief acc acc_c3 register, offset:0x14
*/
union
{
union {
__IO uint32_t c3;
struct
{
struct {
__IO uint32_t c3 : 16;/* [15:0] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} c3_bit;

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