mirror of
https://github.com/RfidResearchGroup/ChameleonMini.git
synced 2026-05-12 11:20:37 -07:00
Federico Cerutti
247a0ffd55
While in the process of writing a new codec I stumbled upon the long standing issue of ISR sharing in AVR MCUs. Actually this is accomplished with an ISR written in C, which simply calls another plain C function referenced via a function pointer updated at runtime. This approach is slow because GCC can't optimize the ISR, since it does not know which registers will be used, so it defaults to push/pop all of them. My solution keeps the concept of pointers to functions, but greatly improves speed by reducing the ISR itself to the bare minimum to call another function, which will be compiled by GCC as a signal. This means all interrupt optimizations will be put in place by GCC, while ISRs can be still written in plain C code, but the overhead is now much smaller. It has proven to reduce by 20 the number of instructions for every ISR, mainly pushes/pops, which cuts the clock cycle count down by 30 cycles (1 cycle for every push, 2 for pop). In time units, this means 1.1 uSec are saved for every ISR invocation and every shared ISR now takes only 13 clock cycles more than the "bare" one. A new ISR_SHARED function type has been defined in Common.h to hide away from the programmer GCC attributes. All new shared interrupt handling routines should be defined of this type to prevent stack and registers corruption. Minor changes were made to Codec.h to allow including it in .S files.
143 lines
3.5 KiB
C
143 lines
3.5 KiB
C
/*
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* System.c
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*
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* Created on: 10.02.2013
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* Author: skuser
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*/
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#include "System.h"
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#include "LED.h"
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#include <avr/interrupt.h>
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#ifndef WDT_PER_500CLK_gc
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#define WDT_PER_500CLK_gc WDT_PER_512CLK_gc
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#endif
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ISR(BADISR_vect) {
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//LED_PORT.OUTSET = LED_RED;
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while (1);
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}
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ISR(RTC_OVF_vect) {
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SYSTEM_TICK_REGISTER += SYSTEM_TICK_PERIOD;
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}
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void SystemInit(void) {
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if (RST.STATUS & RST_WDRF_bm) {
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/* On Watchdog reset clear WDRF bit, disable watchdog
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* and jump into bootloader */
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RST.STATUS = RST_WDRF_bm;
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CCP = CCP_IOREG_gc;
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WDT.CTRL = WDT_CEN_bm;
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asm volatile("jmp %0"::"i"(BOOT_SECTION_START + 0x1FC));
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}
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/* XTAL x 2 as SysCLK */
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OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_16KCLK_gc;
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OSC.CTRL |= OSC_XOSCEN_bm;
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while (!(OSC.STATUS & OSC_XOSCRDY_bm))
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;
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OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | (2 << OSC_PLLFAC_gp);
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OSC.CTRL |= OSC_PLLEN_bm;
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while (!(OSC.STATUS & OSC_PLLRDY_bm))
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;
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/* Set PLL as main clock */
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CCP = CCP_IOREG_gc;
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CLK.CTRL = CLK_SCLKSEL_PLL_gc;
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SYSTEM_TICK_REGISTER = 0;
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/* Enable RTC with roughly 1kHz clock for system tick
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* and to wake up while sleeping. */
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CLK.RTCCTRL = CLK_RTCSRC_ULP_gc | CLK_RTCEN_bm;
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RTC.PER = SYSTEM_TICK_PERIOD - 1;
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RTC.COMP = SYSTEM_TICK_PERIOD - 1;
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RTC.CTRL = RTC_PRESCALER_DIV1_gc;
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RTC.INTCTRL = RTC_OVFINTLVL_LO_gc;
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/* Enable EEPROM data memory mapping */
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//NVM.CTRLB |= NVM_EEMAPEN_bm;
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/* Enable DMA */
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DMA.CTRL = DMA_ENABLE_bm | DMA_DBUFMODE_DISABLED_gc | DMA_PRIMODE_RR0123_gc;
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}
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void SystemReset(void) {
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CCP = CCP_IOREG_gc;
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RST.CTRL = RST_SWRST_bm;
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}
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void SystemEnterBootloader(void) {
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/* Use Watchdog timer to reset into bootloader. */
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CCP = CCP_IOREG_gc;
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WDT.CTRL = WDT_PER_500CLK_gc | WDT_ENABLE_bm | WDT_CEN_bm;
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}
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void SystemStartUSBClock(void) {
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//SystemSleepDisable();
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#if 0
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/* 48MHz USB Clock using 12MHz XTAL */
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OSC.XOSCCTRL = OSC_FRQRANGE_12TO16_gc | OSC_XOSCSEL_XTAL_16KCLK_gc;
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OSC.CTRL |= OSC_XOSCEN_bm;
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while (!(OSC.STATUS & OSC_XOSCRDY_bm))
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;
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OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | (4 << OSC_PLLFAC_gp);
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OSC.CTRL |= OSC_PLLEN_bm;
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while (!(OSC.STATUS & OSC_PLLRDY_bm))
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;
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#else
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/* Use internal HS RC for USB */
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OSC.CTRL |= OSC_RC32MEN_bm;
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while (!(OSC.STATUS & OSC_RC32MRDY_bm))
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;
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/* Load RC32 CAL values for 48MHz use */
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NVM.CMD = NVM_CMD_READ_CALIB_ROW_gc;
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DFLLRC32M.CALA = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSCA));
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DFLLRC32M.CALB = pgm_read_byte(offsetof(NVM_PROD_SIGNATURES_t, USBRCOSC));
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NVM.CMD = NVM_CMD_NO_OPERATION_gc;
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/* For USBSOF operation, whe need to use COMP = 48MHz/1kHz = 0xBB80 */
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DFLLRC32M.COMP1 = 0x80;
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DFLLRC32M.COMP2 = 0xBB;
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/* Select USBSOF as DFLL source */
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OSC.DFLLCTRL &= ~OSC_RC32MCREF_gm;
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OSC.DFLLCTRL |= OSC_RC32MCREF_USBSOF_gc;
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/* Enable DFLL */
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DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
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#endif
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}
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void SystemStopUSBClock(void) {
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//SystemSleepEnable();
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#if 0
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/* Disable USB Clock to minimize power consumption */
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CLK.USBCTRL &= ~CLK_USBSEN_bm;
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OSC.CTRL &= ~OSC_PLLEN_bm;
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OSC.CTRL &= ~OSC_XOSCEN_bm;
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#else
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/* Disable USB Clock to minimize power consumption */
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CLK.USBCTRL &= ~CLK_USBSEN_bm;
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DFLLRC32M.CTRL &= ~DFLL_ENABLE_bm;
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OSC.CTRL &= ~OSC_RC32MEN_bm;
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#endif
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}
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void SystemInterruptInit(void) {
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/* Enable all interrupt levels */
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PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
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sei();
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}
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