14 #include "../Common.h" 15 #include "../Configuration.h" 17 #include "ISO14443-2A.h" 18 #include "Reader14443-2A.h" 21 #define ISO14443A_SUBCARRIER_DIVIDER 16 22 #define ISO14443A_BIT_GRID_CYCLES 128 23 #define ISO14443A_BIT_RATE_CYCLES 128 24 #define ISO14443A_FRAME_DELAY_PREV1 1236 25 #define ISO14443A_FRAME_DELAY_PREV0 1172 26 #define ISO14443A_RX_PENDING_TIMEOUT 1 // ms 29 #define CODEC_DEMOD_POWER_PORT PORTB 30 #define CODEC_DEMOD_POWER_MASK PIN0_bm 31 #define CODEC_DEMOD_IN_PORT PORTB 32 #define CODEC_DEMOD_IN_MASK (CODEC_DEMOD_IN_MASK0 | CODEC_DEMOD_IN_MASK1) 33 #define CODEC_DEMOD_IN_MASK0 PIN1_bm 34 #define CODEC_DEMOD_IN_MASK1 PIN2_bm 35 #define CODEC_DEMOD_IN_PINCTRL0 PIN1CTRL 36 #define CODEC_DEMOD_IN_PINCTRL1 PIN2CTRL 37 #define CODEC_DEMOD_IN_EVMUX0 EVSYS_CHMUX_PORTB_PIN1_gc 38 #define CODEC_DEMOD_IN_EVMUX1 EVSYS_CHMUX_PORTB_PIN2_gc 39 #define CODEC_DEMOD_IN_INT0_VECT PORTB_INT0_vect 40 #define CODEC_LOADMOD_PORT PORTC 41 #define CODEC_LOADMOD_MASK PIN6_bm 42 #define CODEC_CARRIER_IN_PORT PORTC 43 #define CODEC_CARRIER_IN_MASK PIN2_bm 44 #define CODEC_CARRIER_IN_PINCTRL PIN2CTRL 45 #define CODEC_CARRIER_IN_EVMUX EVSYS_CHMUX_PORTC_PIN2_gc 46 #define CODEC_CARRIER_IN_DIV 2 47 #define CODEC_SUBCARRIER_PORT PORTC 48 #define CODEC_SUBCARRIER_MASK_PSK PIN4_bm 49 #define CODEC_SUBCARRIER_MASK_OOK PIN5_bm 50 #define CODEC_SUBCARRIER_MASK (CODEC_SUBCARRIER_MASK_PSK | CODEC_SUBCARRIER_MASK_OOK) 51 #define CODEC_SUBCARRIER_TIMER TCC1 52 #define CODEC_SUBCARRIER_CC_PSK CCA 53 #define CODEC_SUBCARRIER_CC_OOK CCB 54 #define CODEC_SUBCARRIER_CCEN_PSK TC1_CCAEN_bm 55 #define CODEC_SUBCARRIER_CCEN_OOK TC1_CCBEN_bm 56 #define CODEC_TIMER_SAMPLING TCD0 57 #define CODEC_TIMER_SAMPLING_CCA_VECT TCD0_CCA_vect 58 #define CODEC_TIMER_SAMPLING_CCB_VECT TCD0_CCB_vect 59 #define CODEC_TIMER_LOADMOD TCE0 60 #define CODEC_TIMER_LOADMOD_OVF_VECT TCE0_OVF_vect 61 #define CODEC_TIMER_LOADMOD_CCA_VECT TCE0_CCA_vect 62 #define CODEC_TIMER_LOADMOD_CCB_VECT TCE0_CCB_vect 63 #define CODEC_TIMER_LOADMOD_CCC_VECT TCE0_CCC_vect 64 #define CODEC_TIMER_MODSTART_EVSEL TC_EVSEL_CH0_gc 65 #define CODEC_TIMER_MODEND_EVSEL TC_EVSEL_CH1_gc 66 #define CODEC_TIMER_CARRIER_CLKSEL TC_CLKSEL_EVCH6_gc 67 #define CODEC_READER_TIMER TCC0 68 #define CODEC_READER_PORT PORTC 69 #define CODEC_READER_MASK_LEFT PIN0_bm 70 #define CODEC_READER_MASK_RIGHT PIN1_bm 71 #define CODEC_READER_MASK (CODEC_READER_MASK_LEFT | CODEC_READER_MASK_RIGHT) 72 #define CODEC_READER_PINCTRL_LEFT PIN0CTRL 73 #define CODEC_READER_PINCTRL_RIGHT PIN1CTRL 74 #define CODEC_AC_DEMOD_SETTINGS AC_HSMODE_bm | AC_HYSMODE_NO_gc 75 #define CODEC_MAXIMUM_THRESHOLD 0xFFF // the maximum voltage can be calculated with ch0data * Vref / 0xFFF 76 #define CODEC_THRESHOLD_CALIBRATE_MIN 128 77 #define CODEC_THRESHOLD_CALIBRATE_MAX 1024 78 #define CODEC_THRESHOLD_CALIBRATE_STEPS 8 79 #define CODEC_TIMER_TIMESTAMPS TCD1 80 #define CODEC_TIMER_TIMESTAMPS_CCA_VECT TCD1_CCA_vect 82 #define CODEC_BUFFER_SIZE 256 84 #define CODEC_CARRIER_FREQ 13560000 86 #define Codec8Reg0 GPIOR0 87 #define Codec8Reg1 GPIOR1 88 #define Codec8Reg2 GPIOR2 89 #define Codec8Reg3 GPIOR3 90 #define CodecCount16Register1 (*((volatile uint16_t*) &GPIOR4)) 91 #define CodecCount16Register2 (*((volatile uint16_t*) &GPIOR6)) 92 #define CodecPtrRegister1 (*((volatile uint8_t**) &GPIOR8)) 93 #define CodecPtrRegister2 (*((volatile uint8_t**) &GPIORA)) 95 extern uint16_t ReaderThreshold;
96 extern uint16_t Reader_FWT;
98 #define FWI2FWT(x) ((uint32_t)(256 * 16 * ((uint32_t)1 << (x))) / (CODEC_CARRIER_FREQ / 1000) + 1) 101 CODEC_SUBCARRIERMOD_OFF,
102 CODEC_SUBCARRIERMOD_OOK
105 extern uint8_t CodecBuffer[CODEC_BUFFER_SIZE];
107 INLINE
void CodecInit(
void) {
111 INLINE
void CodecDeInit(
void) {
115 INLINE
void CodecTask(
void) {
120 INLINE
void CodecInitCommon(
void)
125 #if CODEC_CARRIER_IN_DIV == 2 126 CODEC_CARRIER_IN_PORT.CODEC_CARRIER_IN_PINCTRL = PORT_ISC_BOTHEDGES_gc;
128 #error Option not supported 130 CODEC_CARRIER_IN_PORT.DIRCLR = CODEC_CARRIER_IN_MASK;
131 EVSYS.CH6MUX = CODEC_CARRIER_IN_EVMUX;
136 CODEC_DEMOD_POWER_PORT.OUTCLR = CODEC_DEMOD_POWER_MASK;
137 CODEC_DEMOD_POWER_PORT.DIRSET = CODEC_DEMOD_POWER_MASK;
138 CODEC_DEMOD_IN_PORT.DIRCLR = CODEC_DEMOD_IN_MASK;
139 CODEC_DEMOD_IN_PORT.CODEC_DEMOD_IN_PINCTRL0 = PORT_ISC_RISING_gc;
140 CODEC_DEMOD_IN_PORT.CODEC_DEMOD_IN_PINCTRL1 = PORT_ISC_FALLING_gc;
141 CODEC_DEMOD_IN_PORT.INT0MASK = 0;
142 CODEC_DEMOD_IN_PORT.INTCTRL = PORT_INT0LVL_HI_gc;
143 EVSYS.CH0MUX = CODEC_DEMOD_IN_EVMUX0;
144 EVSYS.CH1MUX = CODEC_DEMOD_IN_EVMUX1;
148 CODEC_LOADMOD_PORT.DIRSET = CODEC_LOADMOD_MASK;
149 CODEC_LOADMOD_PORT.OUTCLR = CODEC_LOADMOD_MASK;
150 PORTCFG.VPCTRLA &= ~PORTCFG_VP0MAP_gm;
151 PORTCFG.VPCTRLA |= PORTCFG_VP02MAP_PORTC_gc;
154 CODEC_SUBCARRIER_PORT.DIRSET = CODEC_SUBCARRIER_MASK;
155 CODEC_SUBCARRIER_PORT.OUTCLR = CODEC_SUBCARRIER_MASK;
159 CODEC_READER_PORT.CODEC_READER_PINCTRL_LEFT = PORT_INVEN_bm;
160 CODEC_READER_PORT.OUTCLR = CODEC_READER_MASK_LEFT;
161 CODEC_READER_PORT.OUTSET = CODEC_READER_MASK_RIGHT;
162 CODEC_READER_PORT.DIRSET = CODEC_READER_MASK;
166 CODEC_READER_TIMER.CTRLB = TC0_CCAEN_bm | TC_WGMODE_SINGLESLOPE_gc;
167 CODEC_READER_TIMER.PER = F_CPU / CODEC_CARRIER_FREQ - 1;
168 CODEC_READER_TIMER.CCA = F_CPU / CODEC_CARRIER_FREQ / 2 ;
170 AWEXC.OUTOVEN = 0x00;
171 AWEXC.CTRL = AWEX_CWCM_bm | AWEX_DTICCAEN_bm | AWEX_DTICCBEN_bm;
175 DACB.CTRLB = DAC_CHSEL_SINGLE_gc;
176 DACB.CTRLC = DAC_REFSEL_AVCC_gc;
177 DACB.CTRLA = DAC_IDOEN_bm | DAC_ENABLE_bm;
178 DACB.CH0DATA = ReaderThreshold;
181 ACA.AC0MUXCTRL = AC_MUXPOS_DAC_gc | AC_MUXNEG_PIN7_gc;
182 ACA.AC0CTRL = CODEC_AC_DEMOD_SETTINGS;
185 ACA.AC1MUXCTRL = AC_MUXPOS_DAC_gc | AC_MUXNEG_PIN7_gc;
186 ACA.AC1CTRL = CODEC_AC_DEMOD_SETTINGS;
189 INLINE
void CodecSetSubcarrier(SubcarrierModType ModType, uint16_t Divider)
191 if (ModType == CODEC_SUBCARRIERMOD_OFF) {
192 CODEC_SUBCARRIER_TIMER.CTRLA = TC_CLKSEL_OFF_gc;
193 CODEC_SUBCARRIER_TIMER.CTRLB = 0;
194 }
else if (ModType == CODEC_SUBCARRIERMOD_OOK) {
196 CODEC_SUBCARRIER_TIMER.CNT = 0;
197 CODEC_SUBCARRIER_TIMER.PER = Divider - 1;
198 CODEC_SUBCARRIER_TIMER.CODEC_SUBCARRIER_CC_OOK = Divider/2;
199 CODEC_SUBCARRIER_TIMER.CTRLB = CODEC_SUBCARRIER_CCEN_OOK | TC_WGMODE_SINGLESLOPE_gc;
203 INLINE
void CodecStartSubcarrier(
void)
205 CODEC_SUBCARRIER_TIMER.CTRLA = CODEC_TIMER_CARRIER_CLKSEL;
208 INLINE
void CodecSetDemodPower(
bool bOnOff)
211 CODEC_DEMOD_POWER_PORT.OUTSET = CODEC_DEMOD_POWER_MASK;
213 CODEC_DEMOD_POWER_PORT.OUTCLR = CODEC_DEMOD_POWER_MASK;
217 INLINE
bool CodecGetLoadmodState(
void) {
218 if (ACA.STATUS & AC_AC0STATE_bm) {
225 INLINE
void CodecSetLoadmodState(
bool bOnOff) {
227 VPORT0.OUT |= CODEC_LOADMOD_MASK;
229 VPORT0.OUT &= ~CODEC_LOADMOD_MASK;
233 INLINE
void CodecSetReaderField(
bool bOnOff) {
237 CODEC_READER_TIMER.CTRLA = TC_CLKSEL_DIV1_gc;
238 AWEXC.OUTOVEN = CODEC_READER_MASK;
241 AWEXC.OUTOVEN = 0x00;
242 CODEC_READER_TIMER.CTRLA = TC_CLKSEL_OFF_gc;
246 INLINE
bool CodecGetReaderField(
void) {
247 return (CODEC_READER_TIMER.CTRLA == TC_CLKSEL_DIV1_gc) && (AWEXC.OUTOVEN == CODEC_READER_MASK);
250 void CodecReaderFieldStart(
void);
251 void CodecReaderFieldStop(
void);
252 bool CodecIsReaderFieldReady(
void);
254 void CodecReaderFieldRestart(uint16_t delay);
255 #define FIELD_RESTART() CodecReaderFieldRestart(100) 256 bool CodecIsReaderToBeRestarted(
void);
258 void CodecThresholdSet(uint16_t th);
259 uint16_t CodecThresholdIncrement(
void);
260 void CodecThresholdReset(
void);
void(* CodecInitFunc)(void)
Definition: Configuration.h:59
void(* CodecTaskFunc)(void)
Definition: Configuration.h:65
void(* CodecDeInitFunc)(void)
Definition: Configuration.h:61