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45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
#Created by Constraints Editor (xc9572xl-vq44-10) - 2014/05/07
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NET "portLCLK" TNM_NET = portLCLK;
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TIMESPEC TS_portLCLK = PERIOD "portLCLK" 33 MHz HIGH 50%;
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#NET register powerup value
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NET D0enable INIT=R;
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NET direction INIT=R;
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NET iportCT INIT=R;
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NET iportBL INIT=R;
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NET init INIT=R;
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NET EN_5V INIT=R;
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#PACE: Start of Constraints generated by PACE
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#PACE: Start of PACE I/O Pin Assignments
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NET "BNK1" LOC = "P27" ;
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NET "BNK2" LOC = "P28" ;
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NET "EN_5V" LOC = "P41" ;
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NET "fportLAD<0>" LOC = "P23" ;
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NET "fportLAD<1>" LOC = "P19" ;
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NET "fportLAD<2>" LOC = "P22" ;
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NET "fportLAD<3>" LOC = "P21" ;
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NET "nportLRST" LOC = "P39" ;
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NET "portBL" LOC = "P8" ;
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NET "portCT" LOC = "P44" ;
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NET "portD0" LOC = "P32" ;
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NET "portLCD<0>" LOC = "P1" ;
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NET "portLCD<1>" LOC = "P2" ;
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NET "portLCD<2>" LOC = "P3" ;
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NET "portLCD<3>" LOC = "P5" ;
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NET "portLCD<4>" LOC = "P6" ;
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NET "portLCD<5>" LOC = "P7" ;
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NET "portLCLK" LOC = "P43" | BUFG = CLK ;
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NET "portLFRAME" LOC = "P20" ;
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NET "portPWR" LOC = "P42" ;
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NET "xLFRAME" LOC = "P31" ;
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NET "xportLAD<0>" LOC = "P34" ;
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NET "xportLAD<1>" LOC = "P36" ;
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NET "xportLAD<2>" LOC = "P38" ;
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NET "xportLAD<3>" LOC = "P37" ;
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#PACE: Start of PACE Area Constraints
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#PACE: Start of PACE Prohibit Constraints
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#PACE: End of Constraints generated by PACE
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