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  • caab1bbc7c arm: Implement STR reg/imm instructions. bunnei 2016-08-04 19:35:17 -04:00
  • b09ecb4532 arm: Implement LDR reg/imm instructions. bunnei 2016-08-03 16:59:43 -04:00
  • 856298577d EmitX64: Don't give MOVSX or MOVZX an immediate oparg MerryMage 2016-08-06 01:03:39 +01:00
  • 640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} MerryMage 2016-08-05 18:54:19 +01:00
  • d31bbd6d14 Common/x64/CpuDetect: Disable MSVC warning for strncpy MerryMage 2016-08-05 18:42:26 +01:00
  • 4c0a85f3b3 EmitX64: Correct EmitPack2x32To1x64 implementation MerryMage 2016-08-05 18:41:25 +01:00
  • 742eeb8913 BackendX64/RegAlloc: Correct debugging asserts and correct UseDef behaviour for spill locations MerryMage 2016-08-05 18:40:28 +01:00
  • d2aeb56503 Common: DEBUG_ASSERTs weren't enabled MerryMage 2016-08-05 18:39:47 +01:00
  • 6f6f60c61b tests/FuzzArm: Only call raise(SIGTRAP) when __unix__ is defined MerryMage 2016-08-05 16:04:16 +01:00
  • d80dcc5367 BackendX64/EmitX64: Eliminate unnecessary MOVs in Add64, Mul, Mul64, SignExtendWordToLong, ZeroExtendWordToLong, Pack2x32To1x64 MerryMage 2016-08-05 15:27:29 +01:00
  • 2b025183a2 BackendX64/RegAlloc: Correct UseDefRegsiter behaviour for last use MerryMage 2016-08-05 15:24:25 +01:00
  • b4aa01ccf4 Merge remote-tracking branch 'tilkax/master' MerryMage 2016-08-05 14:13:09 +01:00
  • 94e75ad32f BackendX64/EmitX64: Reduce number of MOVs by using reg_alloc.{RegisterAddDef,UseDefOpArg,UseOpArg} MerryMage 2016-08-05 14:11:27 +01:00
  • 92bd5f214b BackendX64/RegAlloc: Add RegisterAddDef, UseDefOpArg, UseOpArg MerryMage 2016-08-05 14:10:39 +01:00
  • 01cfaf0286 IR: Properly support Identity in IR::Value MerryMage 2016-08-05 14:09:10 +01:00
  • ca40015145 IR: Add Breakpoint IR instruction (for debugging purposes, emits a host-breakpoint) MerryMage 2016-08-05 14:07:27 +01:00
  • fce8c86c90 Implement RSB Tillmann Karras 2016-08-05 02:13:26 +01:00
  • eb2e6e8bea Implement some multiplies Tillmann Karras 2016-08-05 02:03:23 +01:00
  • 72c503016c Fix Pack2x32To1x64 Tillmann Karras 2016-08-05 01:57:43 +01:00
  • 3fdc093d10 Add more IR opcodes for multiply instructions Tillmann Karras 2016-08-04 22:04:42 +01:00
  • a97668ead4 Simplify ARM fuzz tests Tillmann Karras 2016-08-05 01:56:35 +01:00
  • 023643b4fa Disable load/store tests for now Tillmann Karras 2016-08-05 02:07:09 +01:00
  • ab383b4be5 Break tests by fixing them Tillmann Karras 2016-08-05 01:51:35 +01:00
  • af27ef8d6c Optionally disassemble x86_64 code using LLVM Tillmann Karras 2016-08-05 01:50:31 +01:00
  • 39563c8ea8 Merged in bunnei/dynarmic (pull request #8) Merry 2016-08-04 13:22:00 +01:00
  • 691e4139fa arm: Implement B/BL/BX instructions. bunnei 2016-08-02 19:52:17 -04:00
  • fc33f1d374 Implement more instructions Tillmann Karras 2016-08-02 10:16:30 +01:00
  • 30a90295b9 Implement data processing instructions Tillmann Karras 2016-08-03 00:44:35 +01:00
  • fe71cc9d78 Disassemble reg-shifted regs in lower case Tillmann Karras 2016-07-31 19:09:25 +01:00
  • 2488926341 Add IR opcode RotateRightExtended Tillmann Karras 2016-07-31 19:07:35 +01:00
  • dacaeadb6a Raise SIGTRAP on non-Windows Tillmann Karras 2016-07-31 19:03:52 +01:00
  • 306e070ab5 Use opcodes.inc for emit_x64.h Tillmann Karras 2016-07-31 14:52:28 +01:00
  • 61eddbd1fa Fix Linux build Tillmann Karras 2016-07-30 23:58:02 +01:00
  • 1252bd653d RegAlloc: Define constructors for HostLocInfo to make MSVC happy MerryMage 2016-08-03 00:25:42 +01:00
  • a875c0c720 TranslateArm: Stub more ARM instructions MerryMage 2016-08-02 21:59:33 +01:00
  • 64c17a2489 tests/FuzzArm: Print out IR upon failure MerryMage 2016-08-02 13:48:06 +01:00
  • deb5e2c10d IR::DumpBlock: Incorrect use of std::map::at MerryMage 2016-08-02 13:47:05 +01:00
  • 4414ec5bc8 RegAlloc: Allow allocation of XMM registers MerryMage 2016-08-02 13:46:12 +01:00
  • 864081d1a0 BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR MerryMage 2016-08-02 12:00:11 +01:00
  • 6097a21955 TranslateArm: Reorganisation - Split visitor into multiple .cpp files MerryMage 2016-08-01 20:20:22 +01:00
  • 93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface MerryMage 2016-08-01 20:03:13 +01:00
  • be87038ffd IROpt: Port get/set elimination pass to current IR MerryMage 2016-08-02 11:51:05 +01:00
  • e60cea3a54 Add -pedantic-errors compilation flag MerryMage 2016-08-01 19:54:31 +01:00
  • cd86ef4236 Add -DBOOST_POOL_NO_MT as a compiler flag MerryMage 2016-07-23 05:37:07 +01:00
  • 51448aa06d More Speed MerryMage 2016-07-22 23:55:00 +01:00
  • 5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) MerryMage 2016-07-21 21:48:45 +01:00
  • 90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. MerryMage 2016-07-20 15:34:17 +01:00
  • 98bd7ff6a5 Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support. MerryMage 2016-07-20 12:08:17 +01:00
  • 95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) Merry 2016-07-20 10:19:55 +01:00
  • 95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates MerryMage 2016-07-18 22:48:23 +01:00
  • 3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) MerryMage 2016-07-18 22:18:58 +01:00
  • fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. Subv 2016-07-18 16:13:33 -05:00
  • 426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH. Subv 2016-07-18 16:13:02 -05:00
  • c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. Subv 2016-07-18 16:10:35 -05:00
  • e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) MerryMage 2016-07-18 21:04:39 +01:00
  • ccc61472b9 Added format strings for ARM STRBT encodings A1 and A2 Subv 2016-07-18 14:20:58 -05:00
  • 8617bf80a1 Added format strings for ARM LDRBT encodings A1 and A2 Subv 2016-07-18 14:18:39 -05:00
  • 5d5ea9325c Added format strings for ARM STRT encodings A1 and A2 Subv 2016-07-18 14:05:53 -05:00
  • 2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. MerryMage 2016-07-18 20:05:35 +01:00
  • 8a310777a1 backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC MerryMage 2016-07-18 20:01:48 +01:00
  • 77761ba032 Added the format strings for LDRT encodings A1 and A2. Subv 2016-07-18 14:01:18 -05:00
  • 14dcb18bbe Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2) MerryMage 2016-07-18 18:48:08 +01:00
  • a605a43ef9 Implement Thumb Instructions: STRH (imm), LDRH (imm) MerryMage 2016-07-18 18:28:52 +01:00
  • f9755870bb Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg) MerryMage 2016-07-18 18:01:15 +01:00
  • 3b8790bf29 Merged in Subv/dynarmic/small_opt (pull request #3) Merry 2016-07-18 17:38:12 +01:00
  • dfef65d98f Implement thumb POP instruction MerryMage 2016-07-18 17:37:48 +01:00
  • 703a46ec99 Pass the current IR::Block by reference to the emitter. Subv 2016-07-18 11:27:33 -05:00
  • f7e3d7b8d2 Implement Thumb PUSH instruction MerryMage 2016-07-18 15:11:16 +01:00
  • 9109b226af Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm) MerryMage 2016-07-18 11:16:12 +01:00
  • c18a3eeab4 Better MSVC support MerryMage 2016-07-18 10:28:17 +01:00
  • bf99ddd065 Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic MerryMage 2016-07-18 10:33:52 +01:00
  • 28a201da16 Implement Thumb ADR instruction MerryMage 2016-07-18 09:25:33 +01:00
  • 6708960aeb Merged in Subv/dynarmic/rev (pull request #2) Merry 2016-07-17 22:13:36 +01:00
  • 0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. Subv 2016-07-17 14:45:42 -05:00
  • 24aa24b1bc Merged in Subv/dynarmic (pull request #1) Merry 2016-07-17 19:43:49 +01:00
  • 7f09510945 Implemented ARM CMP (imm) instruction. Subv 2016-07-17 13:29:37 -05:00
  • 3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} MerryMage 2016-07-16 19:23:42 +01:00
  • 866dce0f23 tests/Thumb: Add revsh (thumb) test MerryMage 2016-07-16 19:22:57 +01:00
  • 22b1bd7cc7 tests/Skyeye: Fix thumb REVSH translation MerryMage 2016-07-16 19:22:09 +01:00
  • 3ef9da9a92 Docs: Design documentation MerryMage 2016-07-15 16:47:13 +01:00
  • 4b1c27e64f Implement arm_ADC_imm MerryMage 2016-07-14 20:02:41 +01:00
  • 63242924fc Implement thumb16_SVC MerryMage 2016-07-14 15:01:30 +01:00
  • 181f78f36e Common: Remove src/common/logging/log.* MerryMage 2016-07-14 14:55:08 +01:00
  • 07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate MerryMage 2016-07-14 14:39:43 +01:00
  • 9b2aff166a Implement arm_SVC MerryMage 2016-07-14 14:04:43 +01:00
  • 672ffb93d0 frontend/translator: Skeleton for Arm translator MerryMage 2016-07-14 13:28:20 +01:00
  • 7d7751c157 Allow IR blocks to require a cond for block entry. MerryMage 2016-07-14 12:52:53 +01:00
  • 4ab4ca58f9 backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight MerryMage 2016-07-14 09:02:27 +01:00
  • 08e848044d backend_x64: Inline Routines::GenReturnFromRunCode into emitted code MerryMage 2016-07-12 16:46:27 +01:00
  • 619b451902 clang support MerryMage 2016-07-12 14:31:43 +01:00
  • 8449deb0bc MSVC support MerryMage 2016-07-12 13:25:33 +01:00
  • 44352680c6 s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones MerryMage 2016-07-12 11:09:34 +01:00
  • 6e46e7899a Translate/Thumb: Fallback to interpreter for Thumb32 instructions MerryMage 2016-07-12 11:02:45 +01:00
  • 60455f9bbc tests/fuzz_thumb: Fuzz instructions that may change the PC MerryMage 2016-07-12 10:58:57 +01:00
  • 09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC MerryMage 2016-07-12 10:58:14 +01:00
  • 65d27f3486 tests: Add some Arm tests MerryMage 2016-07-12 09:12:56 +01:00
  • f85b86486b frontend/TranslateArm: Just interpret all ARM instructions MerryMage 2016-07-12 09:04:47 +01:00
  • 1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg MerryMage 2016-07-11 23:06:35 +01:00
  • e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 MerryMage 2016-07-11 22:43:53 +01:00
  • cbcf61a9e6 backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI MerryMage 2016-07-11 15:28:10 +01:00