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Add support for graphics in nvproxy.

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PiperOrigin-RevId: 708100465
This commit is contained in:
Ayush Ranjan
2024-12-19 17:38:20 -08:00
committed by gVisor bot
parent fb730ff784
commit e6e1ecbdcc
11 changed files with 785 additions and 188 deletions
Download Patch File Download Diff File Expand all files Collapse all files
pkg/abi/nvgpu/classes.go
+43 -3
View File
@@ -35,10 +35,13 @@ func (id ClassID) String() string {
const (
NV01_ROOT = 0x00000000
NV01_ROOT_NON_PRIV = 0x00000001
NV01_EVENT = 0x00000005
NV01_MEMORY_SYSTEM = 0x0000003e
NV01_MEMORY_LOCAL_PRIVILEGED = 0x0000003f
NV01_MEMORY_LOCAL_USER = 0x00000040
NV01_ROOT_CLIENT = 0x00000041
NV_MEMORY_EXTENDED_USER = 0x00000042
NV01_MEMORY_VIRTUAL = 0x00000070
NV01_MEMORY_SYSTEM_OS_DESCRIPTOR = 0x00000071
NV01_EVENT_OS_EVENT = 0x00000079
NV01_DEVICE_0 = 0x00000080
@@ -51,14 +54,20 @@ const (
NV50_THIRD_PARTY_P2P = 0x0000503c
NV50_MEMORY_VIRTUAL = 0x000050a0
GT200_DEBUGGER = 0x000083de
FERMI_TWOD_A = 0x0000902d
FERMI_CONTEXT_SHARE_A = 0x00009067
GF100_DISP_SW = 0x00009072
GF100_ZBC_CLEAR = 0x00009096
GF100_PROFILER = 0x000090cc
GF100_SUBDEVICE_MASTER = 0x000090e6
FERMI_CONTEXT_SHARE_A = 0x00009067
FERMI_VASPACE_A = 0x000090f1
KEPLER_CHANNEL_GROUP_A = 0x0000a06c
KEPLER_INLINE_TO_MEMORY_B = 0x0000a140
VOLTA_USERMODE_A = 0x0000c361
TURING_USERMODE_A = 0x0000c461
TURING_CHANNEL_GPFIFO_A = 0x0000c46f
AMPERE_CHANNEL_GPFIFO_A = 0x0000c56f
TURING_A = 0x0000c597
TURING_DMA_COPY_A = 0x0000c5b5
TURING_COMPUTE_A = 0x0000c5c0
HOPPER_USERMODE_A = 0x0000c661
@@ -74,6 +83,11 @@ const (
HOPPER_COMPUTE_A = 0x0000cbc0
)
// From src/common/sdk/nvidia/inc/class/cl0000.h:
const (
NV01_NULL_OBJECT = 0x0
)
// NV2081_ALLOC_PARAMETERS is the alloc params type for NV2081_BINAPI, from
// src/common/sdk/nvidia/inc/class/cl2081.h.
//
@@ -82,18 +96,34 @@ type NV2081_ALLOC_PARAMETERS struct {
Reserved uint32 `nvproxy:"same"`
}
// NV0005_ALLOC_PARAMETERS is the alloc params type for NV01_EVENT_OS_EVENT,
// NV0005_ALLOC_PARAMETERS is the alloc params type for NV01_EVENT* classes
// from src/common/sdk/nvidia/inc/class/cl0005.h.
//
// +marshal
type NV0005_ALLOC_PARAMETERS struct {
HParentClient Handle `nvproxy:"same"`
HSrcResource Handle
HClass uint32
HClass ClassID
NotifyIndex uint32
Data P64 // actually FD for NV01_EVENT_OS_EVENT, see src/nvidia/src/kernel/rmapi/event.c:eventConstruct_IMPL() => src/nvidia/arch/nvalloc/unix/src/os.c:osUserHandleToKernelPtr()
}
// From src/common/sdk/nvidia/inc/class/cl0070.h:
const (
NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE = 0xffffffff
)
// NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS is the alloc params type for
// NV01_MEMORY_VIRTUAL, from src/common/sdk/nvidia/inc/class/cl0070.h.
//
// +marshal
type NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS struct {
Offset uint64 `nvproxy:"same"`
Limit uint64
HVASpace Handle
Pad0 [4]byte
}
// NV0080_ALLOC_PARAMETERS is the alloc params type for NV01_DEVICE_0, from
// src/common/sdk/nvidia/inc/class/cl0080.h.
//
@@ -317,6 +347,16 @@ type NV_HOPPER_USERMODE_A_PARAMS struct {
Priv uint8
}
// NV9072_ALLOCATION_PARAMETERS is the alloc param type for GF100_DISP_SW,
// from src/common/sdk/nvidia/inc/class/cl9072.h.
//
// +marshal
type NV9072_ALLOCATION_PARAMETERS struct {
LogicalHeadID uint32 `nvproxy:"same"`
DisplayMask uint32
Caps uint32
}
// NV00DE_ALLOC_PARAMETERS is the alloc param type for RM_USER_SHARED_DATA,
// from src/common/sdk/nvidia/inc/class/cl00de.h.
//
pkg/abi/nvgpu/ctrl.go
+124 -72
View File
@@ -30,11 +30,13 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrlxxxx.h:
// NVXXXX_CTRL_XXX_INFO is typedef-ed as the following in the driver:
// - NV0080_CTRL_GR_INFO
// - NV2080_CTRL_FB_INFO
// - NV2080_CTRL_GR_INFO
// - NV2080_CTRL_BIOS_INFO
// - NV0041_CTRL_SURFACE_INFO
//
// +marshal slice:CtrlXxxInfoSlice
// +marshal
type NVXXXX_CTRL_XXX_INFO struct {
Index uint32
Data uint32
@@ -59,17 +61,24 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gpu.h:
const (
NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = 0x201
NV0000_CTRL_CMD_GPU_GET_ID_INFO = 0x202
NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = 0x205
NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = 0x214
NV0000_CTRL_CMD_GPU_ATTACH_IDS = 0x215
NV0000_CTRL_CMD_GPU_DETACH_IDS = 0x216
NV0000_CTRL_CMD_GPU_GET_PCI_INFO = 0x21b
NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = 0x279
NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = 0x27b
NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = 0x289
NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = 0x290
NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS = 0x201
NV0000_CTRL_CMD_GPU_GET_ID_INFO = 0x202
NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS = 0x204
NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2 = 0x205
NV0000_CTRL_CMD_GPU_GET_PROBED_IDS = 0x214
NV0000_CTRL_CMD_GPU_ATTACH_IDS = 0x215
NV0000_CTRL_CMD_GPU_DETACH_IDS = 0x216
NV0000_CTRL_CMD_GPU_GET_PCI_INFO = 0x21b
NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID = 0x275
NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE = 0x279
NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE = 0x27b
NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID = 0x289
NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID = 0x290
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000gsync.h:
const (
NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS = 0x301
)
// NV0000_CTRL_GPU_GET_ID_INFO_PARAMS is the param type for NV0000_CTRL_CMD_GPU_GET_ID_INFO,
@@ -96,6 +105,7 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h:
const (
NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION = 0x101
NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO = 0x102
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS = 0x127
NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2 = 0x12b
NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS = 0x136
@@ -226,41 +236,28 @@ type NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS struct {
OfficialChangelistNumber uint32
}
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080dma.h.
const (
NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS = 0x801806
NV0080_CTRL_CMD_DMA_GET_CAPS = 0x80180d
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl0041.h
const (
NV0041_CTRL_CMD_GET_SURFACE_INFO = 0x410110
)
// +marshal
type NV0041_CTRL_GET_SURFACE_INFO_PARAMS struct {
SurfaceInfoListSize uint32 `nvproxy:"same"`
Pad [4]byte
SurfaceInfoList P64
}
// ListSize implements HasCtrlInfoList.ListSize.
func (p *NV0041_CTRL_GET_SURFACE_INFO_PARAMS) ListSize() uint32 {
return p.SurfaceInfoListSize
}
// SetCtrlInfoList implements HasCtrlInfoList.SetCtrlInfoList.
func (p *NV0041_CTRL_GET_SURFACE_INFO_PARAMS) SetCtrlInfoList(ptr P64) {
p.SurfaceInfoList = ptr
}
// CtrlInfoList implements HasCtrlInfoList.CtrlInfoList.
func (p *NV0041_CTRL_GET_SURFACE_INFO_PARAMS) CtrlInfoList() P64 {
return p.SurfaceInfoList
}
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h:
const (
NV0080_CTRL_CMD_FB_GET_CAPS = 0x801301
NV0080_CTRL_CMD_FB_GET_CAPS_V2 = 0x801307
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fifo.h:
const (
NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = 0x80170d
NV0080_CTRL_CMD_FIFO_GET_CAPS = 0x801701
NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES = 0x801707
NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST = 0x80170d
)
// +marshal
@@ -280,14 +277,35 @@ const (
NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2 = 0x800292
)
// RmapiParamNvU32List is used to represent the following types:
// - NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS
// - NV2080_CTRL_GPU_GET_ENGINES_PARAMS
//
// +marshal
type NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS struct {
NumClasses uint32 `nvproxy:"same"`
Pad [4]byte
ClassList P64
type RmapiParamNvU32List struct {
NumElems uint32
Pad [4]byte
List P64
}
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h:
const (
NV0080_CTRL_CMD_GR_GET_CAPS = 0x801102
NV0080_CTRL_CMD_GR_GET_INFO = 0x801104
)
// NV0080_CTRL_GET_CAPS_PARAMS is used to represent the following:
// - NV0080_CTRL_FB_GET_CAPS_PARAMS
// - NV0080_CTRL_GR_GET_CAPS_PARAMS
// - NV0080_CTRL_FIFO_GET_CAPS_PARAMS
// - NV0080_CTRL_MSENC_GET_CAPS_PARAMS
//
// +marshal
type NV0080_CTRL_GET_CAPS_PARAMS struct {
CapsTblSize uint32
Pad [4]byte
CapsTbl P64
}
// +marshal
type NV0080_CTRL_GR_ROUTE_INFO struct {
@@ -296,6 +314,34 @@ type NV0080_CTRL_GR_ROUTE_INFO struct {
Route uint64
}
// NvxxxCtrlXxxGetInfoParams is used to represent the following:
// - NV0080_CTRL_GR_GET_INFO_PARAMS
// - NV2080_CTRL_FB_GET_INFO_PARAMS
// - NV0041_CTRL_GET_SURFACE_INFO_PARAMS
// - NV2080_CTRL_BIOS_GET_INFO_PARAMS
//
// +marshal
type NvxxxCtrlXxxGetInfoParams struct {
InfoListSize uint32
Pad [4]byte
InfoList P64
}
// ListSize implements HasCtrlInfoList.ListSize.
func (p *NvxxxCtrlXxxGetInfoParams) ListSize() uint32 {
return p.InfoListSize
}
// SetCtrlInfoList implements HasCtrlInfoList.SetCtrlInfoList.
func (p *NvxxxCtrlXxxGetInfoParams) SetCtrlInfoList(ptr P64) {
p.InfoList = ptr
}
// CtrlInfoList implements HasCtrlInfoList.CtrlInfoList.
func (p *NvxxxCtrlXxxGetInfoParams) CtrlInfoList() P64 {
return p.InfoList
}
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h:
const (
NV0080_CTRL_CMD_HOST_GET_CAPS_V2 = 0x801402
@@ -306,6 +352,16 @@ const (
NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL = 0x801909
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080msenc.h:
const (
NV0080_CTRL_CMD_MSENC_GET_CAPS = 0x801b01
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080bsp.h
const (
NV0080_CTRL_CMD_BSP_GET_CAPS_V2 = 0x801c02
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl00f8.h:
const (
NV00F8_CTRL_CMD_ATTACH_MEM = 0xf80103
@@ -331,28 +387,6 @@ const (
NV2080_CTRL_CMD_BIOS_GET_INFO = 0x20800802
)
// +marshal
type NV2080_CTRL_BIOS_GET_INFO_PARAMS struct {
BiosInfoListSize uint32 `nvproxy:"same"`
Pad [4]byte
BiosInfoList P64
}
// ListSize implements HasCtrlInfoList.ListSize.
func (p *NV2080_CTRL_BIOS_GET_INFO_PARAMS) ListSize() uint32 {
return p.BiosInfoListSize
}
// SetCtrlInfoList implements HasCtrlInfoList.SetCtrlInfoList.
func (p *NV2080_CTRL_BIOS_GET_INFO_PARAMS) SetCtrlInfoList(ptr P64) {
p.BiosInfoList = ptr
}
// CtrlInfoList implements HasCtrlInfoList.CtrlInfoList.
func (p *NV2080_CTRL_BIOS_GET_INFO_PARAMS) CtrlInfoList() P64 {
return p.BiosInfoList
}
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h:
const (
NV2080_CTRL_CMD_BUS_GET_PCI_INFO = 0x20801801
@@ -364,7 +398,9 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h:
const (
NV2080_CTRL_CMD_CE_GET_ALL_CAPS = 0x20802a0a
NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK = 0x20802a02
NV2080_CTRL_CMD_CE_GET_CAPS_V2 = 0x20802a03
NV2080_CTRL_CMD_CE_GET_ALL_CAPS = 0x20802a0a
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h:
@@ -374,7 +410,11 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h:
const (
NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303
NV2080_CTRL_CMD_FB_GET_INFO = 0x20801301
NV2080_CTRL_CMD_FB_GET_INFO_V2 = 0x20801303
NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO = 0x20801315
NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO = 0x20801320
NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT = 0x20801352
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h:
@@ -408,12 +448,15 @@ const (
NV2080_CTRL_CMD_GPU_GET_NAME_STRING = 0x20800110
NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING = 0x20800111
NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO = 0x20800119
NV2080_CTRL_CMD_GPU_GET_ENGINES = 0x20800123
NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS = 0x2080012f
NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES = 0x20800131
NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION = 0x20800133
NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO = 0x2080013f
NV2080_CTRL_CMD_GPU_GET_ID = 0x20800142
NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION = 0x20800145 // undocumented; paramSize == 0
NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION = 0x20800146 // undocumented; paramSize == 0
NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST = 0x20800147
NV2080_CTRL_CMD_GPU_GET_GID_INFO = 0x2080014a
NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION = 0x2080014b
NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION = 0x20800156
@@ -429,6 +472,8 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h:
const (
NV2080_CTRL_CMD_GR_GET_INFO = 0x20801201
NV2080_CTRL_CMD_GR_GET_ZCULL_INFO = 0x20801206
NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND = 0x20801208
NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE = 0x20801210
NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE = 0x20801218
NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER = 0x2080121b
@@ -450,25 +495,23 @@ const (
// +marshal
type NV2080_CTRL_GR_GET_INFO_PARAMS struct {
GRInfoListSize uint32 `nvproxy:"same"` // in elements
Pad [4]byte
GRInfoList P64
GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO
NvxxxCtrlXxxGetInfoParams `nvproxy:"same"`
GRRouteInfo NV0080_CTRL_GR_ROUTE_INFO
}
// ListSize implements HasCtrlInfoList.ListSize.
func (p *NV2080_CTRL_GR_GET_INFO_PARAMS) ListSize() uint32 {
return p.GRInfoListSize
return p.InfoListSize
}
// SetCtrlInfoList implements HasCtrlInfoList.SetCtrlInfoList.
func (p *NV2080_CTRL_GR_GET_INFO_PARAMS) SetCtrlInfoList(ptr P64) {
p.GRInfoList = ptr
p.InfoList = ptr
}
// CtrlInfoList implements HasCtrlInfoList.CtrlInfoList.
func (p *NV2080_CTRL_GR_GET_INFO_PARAMS) CtrlInfoList() P64 {
return p.GRInfoList
return p.InfoList
}
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h:
@@ -498,6 +541,7 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080tmr.h:
const (
NV2080_CTRL_CMD_TIMER_GET_TIME = 0x20800403
NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO = 0x20800406
NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ = 0x20800407
)
@@ -525,8 +569,9 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrlc36f.h:
const (
NVC36F_CTRL_GET_CLASS_ENGINEID = 0xc36f0101
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108
NVC36F_CTRL_GET_CLASS_ENGINEID = 0xc36f0101
NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108
NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX = 0xc36f010a
)
// From src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h:
@@ -540,6 +585,12 @@ const (
NV906F_CTRL_CMD_RESET_CHANNEL = 0x906f0102
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl9096.h:
const (
NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE = 0x90960106
NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY = 0x90960107
)
// From src/common/sdk/nvidia/inc/ctrl/ctrl90e6.h:
const (
NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK = 0x90e60102
@@ -555,6 +606,7 @@ const (
// From src/common/sdk/nvidia/inc/ctrl/ctrla06f/ctrla06fgpfifo.h:
const (
NVA06F_CTRL_CMD_GPFIFO_SCHEDULE = 0xa06f0103
NVA06F_CTRL_CMD_BIND = 0xa06f0104
)
// From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h:
pkg/abi/nvgpu/frontend.go
+135 -2
View File
@@ -46,9 +46,13 @@ const (
NV_ESC_RM_ALLOC = 0x2b
NV_ESC_RM_DUP_OBJECT = 0x34
NV_ESC_RM_SHARE = 0x35
NV_ESC_RM_IDLE_CHANNELS = 0x41
NV_ESC_RM_VID_HEAP_CONTROL = 0x4a
NV_ESC_RM_MAP_MEMORY = 0x4e
NV_ESC_RM_UNMAP_MEMORY = 0x4f
NV_ESC_RM_ALLOC_CONTEXT_DMA2 = 0x54
NV_ESC_RM_MAP_MEMORY_DMA = 0x57
NV_ESC_RM_UNMAP_MEMORY_DMA = 0x58
NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO = 0x5e
)
@@ -194,6 +198,17 @@ type NVOS02Parameters struct {
Pad1 [4]byte
}
// Bitfields in NVOS02Parameters.Flags:
const (
NVOS02_FLAGS_ALLOC_SHIFT = 16
NVOS02_FLAGS_ALLOC_MASK = 0x3
NVOS02_FLAGS_ALLOC_NONE = 0x00000001
NVOS02_FLAGS_MAPPING_SHIFT = 30
NVOS02_FLAGS_MAPPING_MASK = 0x3
NVOS02_FLAGS_MAPPING_NO_MAP = 0x00000001
)
// NVOS00Parameters is the parameter type for NV_ESC_RM_FREE.
//
// +marshal
@@ -331,6 +346,31 @@ func (n *NVOS57Parameters) GetStatus() uint32 {
return n.Status
}
// NVOS30Parameters is NVOS30_PARAMETERS, the parameter type for
// NV_ESC_RM_IDLE_CHANNELS.
//
// +marshal
type NVOS30Parameters struct {
Client Handle `nvproxy:"NVOS30_PARAMETERS"`
Device Handle
Channel Handle
NumChannels uint32
Clients P64
Devices P64
Channels P64
Flags uint32
Timeout uint32
Status uint32
Pad0 [4]byte
}
// GetStatus implements HasStatus.GetStatus.
func (n *NVOS30Parameters) GetStatus() uint32 {
return n.Status
}
// NVOS32Parameters is the parameter type for NV_ESC_RM_VID_HEAP_CONTROL.
//
// +marshal
@@ -449,6 +489,96 @@ func (n *NVOS34Parameters) GetStatus() uint32 {
return n.Status
}
// NVOS39Parameters is NVOS39_PARAMETERS, the parameter type for
// NV_ESC_RM_ALLOC_CONTEXT_DMA2.
//
// +marshal
type NVOS39Parameters struct {
HObjectParent Handle `nvproxy:"NVOS39_PARAMETERS"`
HSubDevice Handle
HObjectNew Handle
HClass ClassID
Flags uint32
Selector uint32
HMemory Handle
Pad0 [4]byte
Offset uint64
Limit uint64
Status uint32
Pad1 [4]byte
}
// GetStatus implements HasStatus.GetStatus.
func (n *NVOS39Parameters) GetStatus() uint32 {
return n.Status
}
// NVOS46Parameters is NVOS46_PARAMETERS, the parameter type for
// NV_ESC_RM_MAP_MEMORY_DMA.
//
// +marshal
type NVOS46Parameters struct {
Client Handle `nvproxy:"NVOS46_PARAMETERS"`
Device Handle
Dma Handle
Memory Handle
Offset uint64
Length uint64
Flags uint32
Pad0 [4]byte
DmaOffset uint64
Status uint32
Pad1 [4]byte
}
// GetStatus implements HasStatus.GetStatus.
func (n *NVOS46Parameters) GetStatus() uint32 {
return n.Status
}
// NVOS47Parameters is NVOS47_PARAMETERS, the parameter type for
// NV_ESC_RM_UNMAP_MEMORY_DMA.
//
// +marshal
type NVOS47Parameters struct {
Client Handle `nvproxy:"NVOS47_PARAMETERS"`
Device Handle
Dma Handle
Memory Handle
Flags uint32
Pad0 [4]byte
DmaOffset uint64
Status uint32
Pad1 [4]byte
}
// GetStatus implements HasStatus.GetStatus.
func (n *NVOS47Parameters) GetStatus() uint32 {
return n.Status
}
// NVOS47ParametersV550 is the updated version of NVOS47Parameters since
// 550.54.04.
//
// +marshal
type NVOS47ParametersV550 struct {
Client Handle `nvproxy:"NVOS47_PARAMETERS"`
Device Handle
Dma Handle
Memory Handle
Flags uint32
Pad0 [4]byte
DmaOffset uint64
Size uint64
Status uint32
Pad1 [4]byte
}
// GetStatus implements HasStatus.GetStatus.
func (n *NVOS47ParametersV550) GetStatus() uint32 {
return n.Status
}
// NVOS54Parameters is the parameter type for NV_ESC_RM_CONTROL.
//
// +marshal
@@ -555,11 +685,14 @@ var (
SizeofNVOS00Parameters = uint32((*NVOS00Parameters)(nil).SizeBytes())
SizeofNVOS21Parameters = uint32((*NVOS21Parameters)(nil).SizeBytes())
SizeofIoctlNVOS33ParametersWithFD = uint32((*IoctlNVOS33ParametersWithFD)(nil).SizeBytes())
SizeofNVOS55Parameters = uint32((*NVOS55Parameters)(nil).SizeBytes())
SizeofNVOS57Parameters = uint32((*NVOS57Parameters)(nil).SizeBytes())
SizeofNVOS30Parameters = uint32((*NVOS30Parameters)(nil).SizeBytes())
SizeofNVOS32Parameters = uint32((*NVOS32Parameters)(nil).SizeBytes())
SizeofNVOS34Parameters = uint32((*NVOS34Parameters)(nil).SizeBytes())
SizeofNVOS39Parameters = uint32((*NVOS39Parameters)(nil).SizeBytes())
SizeofNVOS46Parameters = uint32((*NVOS46Parameters)(nil).SizeBytes())
SizeofNVOS54Parameters = uint32((*NVOS54Parameters)(nil).SizeBytes())
SizeofNVOS55Parameters = uint32((*NVOS55Parameters)(nil).SizeBytes())
SizeofNVOS56Parameters = uint32((*NVOS56Parameters)(nil).SizeBytes())
SizeofNVOS57Parameters = uint32((*NVOS57Parameters)(nil).SizeBytes())
SizeofNVOS64Parameters = uint32((*NVOS64Parameters)(nil).SizeBytes())
)
pkg/abi/nvgpu/nvgpu.go
-3
View File
@@ -40,9 +40,6 @@ func (h Handle) String() string {
return fmt.Sprintf("%#x", h.Val)
}
// NV01_NULL_OBJECT is a Handle representing no object.
var NV01_NULL_OBJECT = Handle{0}
// P64 is NvP64, from src/common/sdk/nvidia/inc/nvtypes.h.
//
// +marshal
pkg/sentry/devices/nvproxy/frontend.go
+244 -21
View File
@@ -28,6 +28,7 @@ import (
"gvisor.dev/gvisor/pkg/fdnotifier"
"gvisor.dev/gvisor/pkg/hostarch"
"gvisor.dev/gvisor/pkg/log"
"gvisor.dev/gvisor/pkg/marshal/primitive"
"gvisor.dev/gvisor/pkg/sentry/arch"
"gvisor.dev/gvisor/pkg/sentry/kernel"
"gvisor.dev/gvisor/pkg/sentry/memmap"
@@ -395,6 +396,37 @@ func frontendIoctlHasFD[Params any, PtrParams hasFrontendFDAndStatusPtr[Params]]
return n, nil
}
func rmAllocContextDMA2(fi *frontendIoctlState) (uintptr, error) {
var ioctlParams nvgpu.NVOS39Parameters
if fi.ioctlParamsSize != nvgpu.SizeofNVOS39Parameters {
return 0, linuxerr.EINVAL
}
if _, err := ioctlParams.CopyIn(fi.t, fi.ioctlParamsAddr); err != nil {
return 0, err
}
if log.IsLogging(log.Debug) {
fi.ctx.Debugf("nvproxy: NV_ESC_RM_ALLOC_CONTEXT_DMA2 class %v", ioctlParams.HClass)
}
fi.fd.dev.nvp.objsLock()
n, err := frontendIoctlInvoke(fi, &ioctlParams)
if err == nil && ioctlParams.Status == nvgpu.NV_OK {
// HMemory's parent acts as the parent of the new object. HObjectParent
// acts as the client. See
// src/nvidia/interface/deprecated/rmapi_deprecated_misc.c:RmDeprecatedAllocContextDma().
if _, hMemory := fi.fd.dev.nvp.getObject(fi.ctx, ioctlParams.HObjectParent, ioctlParams.HMemory); hMemory != nil {
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.HObjectParent, ioctlParams.HObjectNew, ioctlParams.HClass, &miscObject{}, hMemory.parent)
}
}
fi.fd.dev.nvp.objsUnlock()
if err != nil {
return n, err
}
if _, err := ioctlParams.CopyOut(fi.t, fi.ioctlParamsAddr); err != nil {
return n, err
}
return n, nil
}
func rmAllocMemory(fi *frontendIoctlState) (uintptr, error) {
var ioctlParams nvgpu.IoctlNVOS02ParametersWithFD
if fi.ioctlParamsSize != nvgpu.SizeofIoctlNVOS02ParametersWithFD {
@@ -411,6 +443,10 @@ func rmAllocMemory(fi *frontendIoctlState) (uintptr, error) {
// src/nvidia/interface/deprecated/rmapi_deprecated_allocmemory.c:rmAllocMemoryTable
// for implementation.
switch ioctlParams.Params.HClass {
case nvgpu.NV01_MEMORY_SYSTEM:
return rmAllocMemorySystem(fi, &ioctlParams)
case nvgpu.NV01_MEMORY_LOCAL_PRIVILEGED, nvgpu.NV01_MEMORY_LOCAL_USER:
return rmAllocMemorySimple(fi, &ioctlParams)
case nvgpu.NV01_MEMORY_SYSTEM_OS_DESCRIPTOR:
return rmAllocOSDescriptor(fi, &ioctlParams)
default:
@@ -419,6 +455,77 @@ func rmAllocMemory(fi *frontendIoctlState) (uintptr, error) {
}
}
func rmAllocMemorySystem(fi *frontendIoctlState, ioctlParams *nvgpu.IoctlNVOS02ParametersWithFD) (uintptr, error) {
// In src/nvidia/arch/nvalloc/unix/src/escape.c:RmIoctl(), see case
// cmd == NV_ESC_RM_ALLOC_MEMORY with pParms->hClass == NV01_MEMORY_SYSTEM.
mapFileGeneric, _ := fi.t.FDTable().Get(ioctlParams.FD)
if mapFileGeneric == nil {
return 0, linuxerr.EINVAL
}
defer mapFileGeneric.DecRef(fi.ctx)
mapFile, ok := mapFileGeneric.Impl().(*frontendFD)
if !ok {
return 0, linuxerr.EINVAL
}
// "If the system memory is going to be mapped immediately, create the mmap
// context for it now."
createMmapCtx :=
// !FLD_TEST_DRF(OS02, _FLAGS, _ALLOC, _NONE, flags))
((ioctlParams.Params.Flags>>nvgpu.NVOS02_FLAGS_ALLOC_SHIFT)&nvgpu.NVOS02_FLAGS_ALLOC_MASK) != nvgpu.NVOS02_FLAGS_ALLOC_NONE &&
// !FLD_TEST_DRF(OS02, _FLAGS, _MAPPING, _NO_MAP, flags))
((ioctlParams.Params.Flags>>nvgpu.NVOS02_FLAGS_MAPPING_SHIFT)&nvgpu.NVOS02_FLAGS_MAPPING_MASK) != nvgpu.NVOS02_FLAGS_MAPPING_NO_MAP
if createMmapCtx {
mapFile.mmapMu.Lock()
defer mapFile.mmapMu.Unlock()
if mapFile.mmapLength != 0 {
fi.ctx.Warningf("nvproxy: attempted to reuse FD %d for NV_ESC_RM_MAP_MEMORY", ioctlParams.FD)
return 0, linuxerr.EINVAL
}
}
origFD := ioctlParams.FD
ioctlParams.FD = mapFile.hostFD
fi.fd.dev.nvp.objsLock()
n, err := frontendIoctlInvoke(fi, ioctlParams)
if err == nil && ioctlParams.Params.Status == nvgpu.NV_OK {
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.Params.HRoot, ioctlParams.Params.HObjectNew, ioctlParams.Params.HClass, &miscObject{}, ioctlParams.Params.HObjectParent)
if createMmapCtx {
mapFile.mmapLength = ioctlParams.Params.Limit + 1
}
}
fi.fd.dev.nvp.objsUnlock()
ioctlParams.FD = origFD
if err != nil {
return n, err
}
if _, err := ioctlParams.CopyOut(fi.t, fi.ioctlParamsAddr); err != nil {
return n, err
}
return n, nil
}
func rmAllocMemorySimple(fi *frontendIoctlState, ioctlParams *nvgpu.IoctlNVOS02ParametersWithFD) (uintptr, error) {
// These shouldn't use ioctlParams.FD; clobber it to be sure.
origFD := ioctlParams.FD
ioctlParams.FD = -1
fi.fd.dev.nvp.objsLock()
n, err := frontendIoctlInvoke(fi, ioctlParams)
if err == nil && ioctlParams.Params.Status == nvgpu.NV_OK {
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.Params.HRoot, ioctlParams.Params.HObjectNew, ioctlParams.Params.HClass, &miscObject{}, ioctlParams.Params.HObjectParent)
}
fi.fd.dev.nvp.objsUnlock()
ioctlParams.FD = origFD
if err != nil {
return n, err
}
if _, err := ioctlParams.CopyOut(fi.t, fi.ioctlParamsAddr); err != nil {
return n, err
}
return n, nil
}
func rmAllocOSDescriptor(fi *frontendIoctlState, ioctlParams *nvgpu.IoctlNVOS02ParametersWithFD) (uintptr, error) {
// Compare src/nvidia/arch/nvalloc/unix/src/escape.c:RmAllocOsDescriptor()
// => RmCreateOsDescriptor().
@@ -497,7 +604,7 @@ func rmAllocOSDescriptor(fi *frontendIoctlState, ioctlParams *nvgpu.IoctlNVOS02P
if err == nil && ioctlParams.Params.Status == nvgpu.NV_OK {
// Transfer ownership of pinned pages to an osDescMem object, to be
// unpinned when the driver OsDescMem is freed.
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.Params.HRoot, ioctlParams.Params.HObjectNew, nvgpu.NV01_MEMORY_SYSTEM_OS_DESCRIPTOR, &osDescMem{
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.Params.HRoot, ioctlParams.Params.HObjectNew, ioctlParams.Params.HClass, &osDescMem{
pinnedRanges: prs,
}, ioctlParams.Params.HObjectParent)
unpinCleanup.Release()
@@ -714,6 +821,26 @@ func ctrlMemoryMulticastFabricAttachGPU(fi *frontendIoctlState, ioctlParams *nvg
return n, err
}
// Check parameter size against the limit of how much can be copied in. It
// returns true if the param size is within limit. If not, caller should return
// NV_ERR_INVALID_ARGUMENT status to the application. Compare
// src/nvidia/src/kernel/rmapi/param_copy.c:rmapiParamsAcquire().
// To find `numElems` and `sizeOfElem` values for a given control command, see
// src/nvidia/src/kernel/rmapi/embedded_param_copy.c:embeddedParamCopyIn() =>
// case <CONTROL CMD> => RMAPI_PARAM_COPY_INIT(..., numElems, sizeOfElem).
func rmapiParamsSizeCheck(numElems uint32, sizeOfElem uint32) bool {
if numElems == 0 {
// The individual implementations of rmapi commands return
// NV_ERR_INVALID_ARGUMENT when numElems is 0. Some examples are:
// - subdeviceCtrlCmdFbGetInfo_IMPL()
// - deviceCtrlCmdKGrGetInfo_IMPL() => _kgraphicsCtrlCmdGrGetInfoV2()
return false
}
// Cast to uint64 to handle overflows. In the driver, this is handled by
// portSafeMulU32().
return uint64(numElems)*uint64(sizeOfElem) <= nvgpu.RMAPI_PARAM_COPY_MAX_PARAMS_SIZE
}
func ctrlClientSystemGetBuildVersion(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters) (uintptr, error) {
var ctrlParams nvgpu.NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS
if ctrlParams.SizeBytes() != int(ioctlParams.ParamsSize) {
@@ -752,35 +879,46 @@ func ctrlClientSystemGetBuildVersion(fi *frontendIoctlState, ioctlParams *nvgpu.
return n, nil
}
func ctrlDevGpuGetClasslist(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters) (uintptr, error) {
var ctrlParams nvgpu.NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS
func ctrlGetNvU32List(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters) (uintptr, error) {
var ctrlParams nvgpu.RmapiParamNvU32List
if ctrlParams.SizeBytes() != int(ioctlParams.ParamsSize) {
return 0, linuxerr.EINVAL
}
if _, err := ctrlParams.CopyIn(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
return 0, err
}
// This command has two modes. If the classList pointer is NULL, only simple command handling
// is required; see src/common/sdk/nvidia/inc/ctrl/ctrl0080gpu.h.
if ctrlParams.ClassList == 0 {
if ctrlParams.List == 0 {
// For NV0080_CTRL_CMD_GPU_GET_CLASSLIST, this command has two modes. If
// the classList pointer is NULL, only simple command handling is required;
// see src/common/sdk/nvidia/inc/ctrl/ctrl0080gpu.h.
return rmControlSimple(fi, ioctlParams)
}
// classList pointer is not NULL. Check classList size against limit. See
// src/nvidia/src/kernel/rmapi/embedded_param_copy.c:embeddedParamCopyIn() =>
// case NV0080_CTRL_CMD_GPU_GET_CLASSLIST => RMAPI_PARAM_COPY_INIT().
// paramCopy.paramsSize is initialized as numClasses * sizeof(NvU32).
if ctrlParams.NumClasses*4 > nvgpu.RMAPI_PARAM_COPY_MAX_PARAMS_SIZE {
if !rmapiParamsSizeCheck(ctrlParams.NumElems, 4 /* sizeof(NvU32) */) {
return 0, ctrlCmdFailWithStatus(fi, ioctlParams, nvgpu.NV_ERR_INVALID_ARGUMENT)
}
classList := make([]uint32, ctrlParams.NumClasses)
n, err := ctrlDevGpuGetClasslistInvoke(fi, ioctlParams, &ctrlParams, classList)
if err != nil {
return n, err
list := make([]uint32, ctrlParams.NumElems)
if _, err := primitive.CopyUint32SliceIn(fi.t, addrFromP64(ctrlParams.List), list); err != nil {
return 0, err
}
return n, nil
return ctrlGetNvU32ListInvoke(fi, ioctlParams, &ctrlParams, list)
}
func ctrlDevGetCaps(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters) (uintptr, error) {
var ctrlParams nvgpu.NV0080_CTRL_GET_CAPS_PARAMS
if ctrlParams.SizeBytes() != int(ioctlParams.ParamsSize) {
return 0, linuxerr.EINVAL
}
if _, err := ctrlParams.CopyIn(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
return 0, err
}
if !rmapiParamsSizeCheck(ctrlParams.CapsTblSize, 1) {
return 0, ctrlCmdFailWithStatus(fi, ioctlParams, nvgpu.NV_ERR_INVALID_ARGUMENT)
}
capsTbl := make([]byte, ctrlParams.CapsTblSize)
// No need to copy into capsTbl from ctrlParams.CapsTbl. All callers specify
// RMAPI_PARAM_COPY_FLAGS_SKIP_COPYIN and RMAPI_PARAM_COPY_FLAGS_ZERO_BUFFER
// in src/nvidia/src/kernel/rmapi/embedded_param_copy.c:embeddedParamCopyIn().
return ctrlDevGRGetCapsInvoke(fi, ioctlParams, &ctrlParams, capsTbl)
}
func ctrlRegisterVASpace(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters) (uintptr, error) {
@@ -872,6 +1010,9 @@ func rmAlloc(fi *frontendIoctlState) (uintptr, error) {
ioctlParams := buf.ToOS64()
// hClass determines the type of pAllocParms.
if err := fixupHClass(fi, &ioctlParams); err != nil {
return 0, err
}
if log.IsLogging(log.Debug) {
fi.ctx.Debugf("nvproxy: allocation class %v", ioctlParams.HClass)
}
@@ -906,6 +1047,25 @@ func rmAlloc(fi *frontendIoctlState) (uintptr, error) {
return result, err
}
// See src/nvidia/src/kernel/rmapi/alloc_free.c:_fixupAllocParams().
func fixupHClass(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters) error {
// "NV01_EVENT isn't a valid class to allocate so overwrite it with the
// subclass from the event params."
if ioctlParams.HClass == nvgpu.NV01_EVENT {
var allocParams nvgpu.NV0005_ALLOC_PARAMETERS
if _, err := allocParams.CopyIn(fi.t, addrFromP64(ioctlParams.PAllocParms)); err != nil {
return err
}
if ioctlParams.HClass != allocParams.HClass {
if log.IsLogging(log.Debug) {
fi.ctx.Debugf("nvproxy: overwriting allocation class %#08x with %#08x", ioctlParams.HClass, allocParams.HClass)
}
ioctlParams.HClass = allocParams.HClass
}
}
return nil
}
// rmAllocSimple implements NV_ESC_RM_ALLOC for classes whose parameters don't
// contain any pointers or file descriptors requiring translation, and whose
// objects require no special handling and depend only on their parents.
@@ -954,7 +1114,7 @@ func rmAllocNoParams(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters
func rmAllocRootClient(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters, isNVOS64 bool) (uintptr, error) {
return rmAllocSimpleParams(fi, ioctlParams, isNVOS64, func(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters, rightsRequested nvgpu.RS_ACCESS_MASK, allocParams *nvgpu.Handle) {
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.HRoot, ioctlParams.HObjectNew, ioctlParams.HClass, newRootClient(fi.fd, ioctlParams, rightsRequested, allocParams), nvgpu.NV01_NULL_OBJECT /* parentH */)
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.HRoot, ioctlParams.HObjectNew, ioctlParams.HClass, newRootClient(fi.fd, ioctlParams, rightsRequested, allocParams), nvgpu.Handle{Val: nvgpu.NV01_NULL_OBJECT} /* parentH */)
if fi.fd.clients == nil {
fi.fd.clients = make(map[nvgpu.Handle]struct{})
}
@@ -993,6 +1153,22 @@ func rmAllocEventOSEvent(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parame
return n, nil
}
func rmAllocMemoryVirtual(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters, isNVOS64 bool) (uintptr, error) {
return rmAllocSimpleParams(fi, ioctlParams, isNVOS64, func(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters, rightsRequested nvgpu.RS_ACCESS_MASK, allocParams *nvgpu.NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS) {
// See
// src/nvidia/src/kernel/mem_mgr/virt_mem_range.c:vmrangeConstruct_IMPL()
// => refAddDependant().
hvaSpace := allocParams.HVASpace
if allocParams.HVASpace.Val == nvgpu.NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE {
// hvaSpace is not added as a dependency when it is
// NV_MEMORY_VIRTUAL_SYSMEM_DYNAMIC_HVASPACE or NV01_NULL_OBJECT. Set it
// to NV01_NULL_OBJECT, which is ignored in nvp.objAdd().
hvaSpace.Val = nvgpu.NV01_NULL_OBJECT
}
fi.fd.dev.nvp.objAdd(fi.ctx, ioctlParams.HRoot, ioctlParams.HObjectNew, ioctlParams.HClass, newRmAllocObject(fi.fd, ioctlParams, rightsRequested, allocParams), ioctlParams.HObjectParent, hvaSpace)
})
}
func rmAllocSMDebuggerSession(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters, isNVOS64 bool) (uintptr, error) {
return rmAllocSimpleParams(fi, ioctlParams, isNVOS64, func(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parameters, rightsRequested nvgpu.RS_ACCESS_MASK, allocParams *nvgpu.NV83DE_ALLOC_PARAMETERS) {
// Compare
@@ -1048,6 +1224,51 @@ func rmAllocContextShare(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64Parame
})
}
// See src/nvidia/interface/deprecated/rmapi_deprecated_misc.c:RmDeprecatedIdleChannels().
func rmIdleChannels(fi *frontendIoctlState) (uintptr, error) {
var ioctlParams nvgpu.NVOS30Parameters
if fi.ioctlParamsSize != nvgpu.SizeofNVOS30Parameters {
return 0, linuxerr.EINVAL
}
if _, err := ioctlParams.CopyIn(fi.t, fi.ioctlParamsAddr); err != nil {
return 0, err
}
if ioctlParams.NumChannels == 0 {
return rmIdleChannelsInvoke(fi, &ioctlParams, nil, nil, nil)
}
if !rmapiParamsSizeCheck(ioctlParams.NumChannels, 4 /* sizeof(NvU32) */) {
log.Warningf("nvproxy: NV_ESC_RM_IDLE_CHANNELS: NumChannels %d is too large", ioctlParams.NumChannels)
return 0, linuxerr.EINVAL
}
bufferSize := ioctlParams.NumChannels * 4
clientsBuf := make([]byte, bufferSize)
if _, err := fi.t.CopyInBytes(addrFromP64(ioctlParams.Clients), clientsBuf); err != nil {
return 0, err
}
devicesBuf := make([]byte, bufferSize)
if _, err := fi.t.CopyInBytes(addrFromP64(ioctlParams.Devices), devicesBuf); err != nil {
return 0, err
}
channelsBuf := make([]byte, bufferSize)
if _, err := fi.t.CopyInBytes(addrFromP64(ioctlParams.Channels), channelsBuf); err != nil {
return 0, err
}
n, err := rmIdleChannelsInvoke(fi, &ioctlParams, &clientsBuf[0], &devicesBuf[0], &channelsBuf[0])
if err != nil {
return n, err
}
if _, err := fi.t.CopyOutBytes(addrFromP64(ioctlParams.Clients), clientsBuf); err != nil {
return n, err
}
if _, err := fi.t.CopyOutBytes(addrFromP64(ioctlParams.Devices), devicesBuf); err != nil {
return n, err
}
if _, err := fi.t.CopyOutBytes(addrFromP64(ioctlParams.Channels), channelsBuf); err != nil {
return n, err
}
return n, nil
}
func rmVidHeapControl(fi *frontendIoctlState) (uintptr, error) {
var ioctlParams nvgpu.NVOS32Parameters
if fi.ioctlParamsSize != nvgpu.SizeofNVOS32Parameters {
@@ -1104,7 +1325,9 @@ func rmMapMemory(fi *frontendIoctlState) (uintptr, error) {
if err != nil {
return n, err
}
mapFile.mmapLength = ioctlParams.Params.Length
if ioctlParams.Params.Status == nvgpu.NV_OK {
mapFile.mmapLength = ioctlParams.Params.Length
}
ioctlParams.FD = origFD
if _, err := ioctlParams.CopyOut(fi.t, fi.ioctlParamsAddr); err != nil {
pkg/sentry/devices/nvproxy/frontend_mmap_unsafe.go
+1 -1
View File
@@ -36,7 +36,7 @@ func (mf *frontendFDMemmapFile) MapInternal(fr memmap.FileRange, at hostarch.Acc
if mf.fd.mmapInternal == 0 {
if mf.fd.mmapLength == 0 {
// This shouldn't be possible.
log.Traceback("nvproxy: frontendFDMemmapFile.MapInternal() called before NV_ESC_RM_MAP_MEMORY")
log.Traceback("nvproxy: frontendFDMemmapFile.MapInternal() called before NV_ESC_RM_MAP_MEMORY or NV_ESC_RM_ALLOC_MEMORY+NV01_MEMORY_SYSTEM")
return safemem.BlockSeq{}, linuxerr.EINVAL
}
// Nvidia kernel driver:
pkg/sentry/devices/nvproxy/frontend_unsafe.go
+48 -8
View File
@@ -96,6 +96,9 @@ func ctrlIoctlHasInfoList[Params any, PtrParams hasCtrlInfoListPtr[Params]](fi *
}
var infoList []byte
if listSize := ctrlParams.ListSize(); listSize > 0 {
if !rmapiParamsSizeCheck(listSize, nvgpu.CtrlXxxInfoSize) {
return 0, ctrlCmdFailWithStatus(fi, ioctlParams, nvgpu.NV_ERR_INVALID_ARGUMENT)
}
infoList = make([]byte, listSize*nvgpu.CtrlXxxInfoSize)
if _, err := fi.t.CopyInBytes(addrFromP64(ctrlParams.CtrlInfoList()), infoList); err != nil {
return 0, err
@@ -126,16 +129,33 @@ func ctrlIoctlHasInfoList[Params any, PtrParams hasCtrlInfoListPtr[Params]](fi *
return n, nil
}
func ctrlDevGpuGetClasslistInvoke(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters, ctrlParams *nvgpu.NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS, classList []uint32) (uintptr, error) {
origClassList := ctrlParams.ClassList
ctrlParams.ClassList = p64FromPtr(unsafe.Pointer(&classList[0]))
func ctrlGetNvU32ListInvoke(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters, ctrlParams *nvgpu.RmapiParamNvU32List, list []uint32) (uintptr, error) {
origList := ctrlParams.List
ctrlParams.List = p64FromPtr(unsafe.Pointer(&list[0]))
n, err := rmControlInvoke(fi, ioctlParams, ctrlParams)
ctrlParams.ClassList = origClassList
ctrlParams.List = origList
if err != nil {
return n, err
}
if _, err := primitive.CopyUint32SliceOut(fi.t, addrFromP64(origClassList), classList); err != nil {
return 0, err
if _, err := primitive.CopyUint32SliceOut(fi.t, addrFromP64(ctrlParams.List), list); err != nil {
return n, err
}
if _, err := ctrlParams.CopyOut(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
return n, err
}
return n, nil
}
func ctrlDevGRGetCapsInvoke(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54Parameters, ctrlParams *nvgpu.NV0080_CTRL_GET_CAPS_PARAMS, capsTbl []byte) (uintptr, error) {
origCapsTbl := ctrlParams.CapsTbl
ctrlParams.CapsTbl = p64FromPtr(unsafe.Pointer(&capsTbl[0]))
n, err := rmControlInvoke(fi, ioctlParams, ctrlParams)
ctrlParams.CapsTbl = origCapsTbl
if err != nil {
return n, err
}
if _, err := primitive.CopyByteSliceOut(fi.t, addrFromP64(ctrlParams.CapsTbl), capsTbl); err != nil {
return n, err
}
if _, err := ctrlParams.CopyOut(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
return n, err
@@ -177,10 +197,10 @@ func ctrlDevFIFOGetChannelList(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS54
}
if _, err := primitive.CopyUint32SliceOut(fi.t, addrFromP64(origPChannelHandleList), channelHandleList); err != nil {
return 0, err
return n, err
}
if _, err := primitive.CopyUint32SliceOut(fi.t, addrFromP64(origPChannelList), channelList); err != nil {
return 0, err
return n, err
}
if _, err := ctrlParams.CopyOut(fi.t, addrFromP64(ioctlParams.Params)); err != nil {
return n, err
@@ -328,6 +348,26 @@ func rmAllocInvoke[Params any](fi *frontendIoctlState, ioctlParams *nvgpu.NVOS64
return n, nil
}
func rmIdleChannelsInvoke(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS30Parameters, clientsBuf, devicesBuf, channelsBuf *byte) (uintptr, error) {
origClients := ioctlParams.Clients
origDevices := ioctlParams.Devices
origChannels := ioctlParams.Channels
ioctlParams.Clients = p64FromPtr(unsafe.Pointer(clientsBuf))
ioctlParams.Devices = p64FromPtr(unsafe.Pointer(devicesBuf))
ioctlParams.Channels = p64FromPtr(unsafe.Pointer(channelsBuf))
n, err := frontendIoctlInvoke(fi, ioctlParams)
ioctlParams.Clients = origClients
ioctlParams.Devices = origDevices
ioctlParams.Channels = origChannels
if err != nil {
return n, err
}
if _, err := ioctlParams.CopyOut(fi.t, fi.ioctlParamsAddr); err != nil {
return n, err
}
return n, nil
}
func rmVidHeapControlAllocSize(fi *frontendIoctlState, ioctlParams *nvgpu.NVOS32Parameters) (uintptr, error) {
allocSizeParams := (*nvgpu.NVOS32AllocSize)(unsafe.Pointer(&ioctlParams.Data))
origAddress := allocSizeParams.Address
pkg/sentry/devices/nvproxy/nvconf/caps.go
+1 -1
View File
@@ -47,7 +47,7 @@ const (
// SupportedDriverCaps is the set of driver capabilities that are supported by
// nvproxy. Similar to
// nvidia-container-toolkit/internal/config/image/capabilities.go:SupportedDriverCapabilities.
SupportedDriverCaps = DriverCaps(CapCompute | CapUtility)
SupportedDriverCaps = DriverCaps(CapCompute | CapUtility | CapGraphics)
// DefaultDriverCaps is the set of driver capabilities that are enabled by
// default in the absence of any other configuration. See
pkg/sentry/devices/nvproxy/object.go
+19 -11
View File
@@ -78,7 +78,7 @@ func (nvp *nvproxy) objsUnlock() {
// freeing of any of those objects also results in the freeing of the recorded
// object.
func (nvp *nvproxy) objAdd(ctx context.Context, clientH, h nvgpu.Handle, c nvgpu.ClassID, oi objectImpl, parentH nvgpu.Handle, deps ...nvgpu.Handle) {
if h == nvgpu.NV01_NULL_OBJECT {
if h.Val == nvgpu.NV01_NULL_OBJECT {
log.Traceback("nvproxy: new object (class %v) has invalid handle %v", c, h)
return
}
@@ -114,7 +114,7 @@ func (nvp *nvproxy) objAdd(ctx context.Context, clientH, h nvgpu.Handle, c nvgpu
}
client.resources[h] = o
if parentH != nvgpu.NV01_NULL_OBJECT {
if parentH.Val != nvgpu.NV01_NULL_OBJECT {
parent, ok := client.resources[parentH]
if !ok {
log.Traceback("nvproxy: new object %v:%v (class %v) has invalid parent handle %v", clientH, h, c, parentH)
@@ -123,7 +123,7 @@ func (nvp *nvproxy) objAdd(ctx context.Context, clientH, h nvgpu.Handle, c nvgpu
}
}
for _, depH := range deps {
if depH == nvgpu.NV01_NULL_OBJECT {
if depH.Val == nvgpu.NV01_NULL_OBJECT {
continue
}
dep, ok := client.resources[depH]
@@ -180,14 +180,8 @@ func (nvp *nvproxy) objDep(o1, o2 *object) {
// client with handle clientSrcH, to handle dstH in the client with handle
// clientDstH, with new parent parentDstH.
func (nvp *nvproxy) objDup(ctx context.Context, clientDstH, dstH, parentDstH, clientSrcH, srcH nvgpu.Handle) {
clientSrc, ok := nvp.clients[clientSrcH]
if !ok {
ctx.Warningf("nvproxy: duplicating object handle %v with unknown client handle %v", srcH, clientSrcH)
return
}
oSrc, ok := clientSrc.resources[srcH]
if !ok {
ctx.Warningf("nvproxy: duplicating object with unknown handle %v:%v", clientSrcH, srcH)
clientSrc, oSrc := nvp.getObject(ctx, clientSrcH, srcH)
if oSrc == nil {
return
}
oDst := &miscObject{}
@@ -201,6 +195,20 @@ func (nvp *nvproxy) objDup(ctx context.Context, clientDstH, dstH, parentDstH, cl
}
}
func (nvp *nvproxy) getObject(ctx context.Context, clientH, h nvgpu.Handle) (*rootClient, *object) {
client, ok := nvp.clients[clientH]
if !ok {
ctx.Warningf("nvproxy: failed to get handle %v with unknown client handle %v", h, clientH)
return nil, nil
}
o, ok := client.resources[h]
if !ok {
ctx.Warningf("nvproxy: failed to get object with unknown handle %v:%v", clientH, h)
return client, nil
}
return client, o
}
// objFree marks an object and its transitive dependents as freed.
//
// Compare
pkg/sentry/devices/nvproxy/seccomp_filters.go
+5 -1
View File
@@ -49,15 +49,19 @@ func frontendIoctlFilters(enabledCaps nvconf.DriverCaps) []seccomp.SyscallRule {
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_FREE_OS_EVENT, nvgpu.SizeofIoctlFreeOSEvent)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_SYS_PARAMS, nvgpu.SizeofIoctlSysParams)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_WAIT_OPEN_COMPLETE, nvgpu.SizeofIoctlWaitOpenComplete)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_ALLOC_MEMORY, nvgpu.SizeofIoctlNVOS02ParametersWithFD)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_ALLOC_MEMORY, nvgpu.SizeofIoctlNVOS02ParametersWithFD)), compUtil | nvconf.CapGraphics},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_FREE, nvgpu.SizeofNVOS00Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_CONTROL, nvgpu.SizeofNVOS54Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_ALLOC, nvgpu.SizeofNVOS64Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_DUP_OBJECT, nvgpu.SizeofNVOS55Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_SHARE, nvgpu.SizeofNVOS57Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_IDLE_CHANNELS, nvgpu.SizeofNVOS30Parameters)), nvconf.CapGraphics},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_VID_HEAP_CONTROL, nvgpu.SizeofNVOS32Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_MAP_MEMORY, nvgpu.SizeofIoctlNVOS33ParametersWithFD)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_UNMAP_MEMORY, nvgpu.SizeofNVOS34Parameters)), compUtil},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_ALLOC_CONTEXT_DMA2, nvgpu.SizeofNVOS39Parameters)), nvconf.CapGraphics},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_MAP_MEMORY_DMA, nvgpu.SizeofNVOS46Parameters)), nvconf.CapGraphics},
{seccomp.MaskedEqual(notIocSizeMask, frontendIoctlCmd(nvgpu.NV_ESC_RM_UNMAP_MEMORY_DMA, 0)), nvconf.CapGraphics},
{seccomp.EqualTo(frontendIoctlCmd(nvgpu.NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO, nvgpu.SizeofNVOS56Parameters)), compUtil},
} {
if feIoctl.caps&enabledCaps != 0 {
pkg/sentry/devices/nvproxy/version.go
+165 -65
View File
@@ -22,6 +22,7 @@ import (
"strings"
"gvisor.dev/gvisor/pkg/abi/nvgpu"
"gvisor.dev/gvisor/pkg/sentry/devices/nvproxy/nvconf"
"gvisor.dev/gvisor/pkg/sync"
)
@@ -183,15 +184,19 @@ func Init() {
nvgpu.NV_ESC_RM_DUP_OBJECT: feHandler(rmDupObject, compUtil),
nvgpu.NV_ESC_RM_SHARE: feHandler(frontendIoctlSimple[nvgpu.NVOS57Parameters], compUtil),
nvgpu.NV_ESC_RM_UNMAP_MEMORY: feHandler(frontendIoctlSimple[nvgpu.NVOS34Parameters], compUtil),
nvgpu.NV_ESC_RM_MAP_MEMORY_DMA: feHandler(frontendIoctlSimple[nvgpu.NVOS46Parameters], nvconf.CapGraphics),
nvgpu.NV_ESC_RM_UNMAP_MEMORY_DMA: feHandler(frontendIoctlSimple[nvgpu.NVOS47Parameters], nvconf.CapGraphics),
nvgpu.NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO: feHandler(frontendIoctlSimple[nvgpu.NVOS56Parameters], compUtil),
nvgpu.NV_ESC_REGISTER_FD: feHandler(frontendRegisterFD, compUtil),
nvgpu.NV_ESC_ALLOC_OS_EVENT: feHandler(frontendIoctlHasFD[nvgpu.IoctlAllocOSEvent], compUtil),
nvgpu.NV_ESC_FREE_OS_EVENT: feHandler(frontendIoctlHasFD[nvgpu.IoctlFreeOSEvent], compUtil),
nvgpu.NV_ESC_NUMA_INFO: feHandler(rmNumaInfo, compUtil),
nvgpu.NV_ESC_RM_ALLOC_MEMORY: feHandler(rmAllocMemory, compUtil),
nvgpu.NV_ESC_RM_ALLOC_CONTEXT_DMA2: feHandler(rmAllocContextDMA2, nvconf.CapGraphics),
nvgpu.NV_ESC_RM_ALLOC_MEMORY: feHandler(rmAllocMemory, compUtil|nvconf.CapGraphics),
nvgpu.NV_ESC_RM_FREE: feHandler(rmFree, compUtil),
nvgpu.NV_ESC_RM_CONTROL: feHandler(rmControl, compUtil),
nvgpu.NV_ESC_RM_ALLOC: feHandler(rmAlloc, compUtil),
nvgpu.NV_ESC_RM_IDLE_CHANNELS: feHandler(rmIdleChannels, nvconf.CapGraphics),
nvgpu.NV_ESC_RM_VID_HEAP_CONTROL: feHandler(rmVidHeapControl, compUtil),
nvgpu.NV_ESC_RM_MAP_MEMORY: feHandler(rmMapMemory, compUtil),
},
@@ -229,77 +234,96 @@ func Init() {
nvgpu.NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_PROBED_IDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_ATTACH_IDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_DETACH_IDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_PCI_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_FEATURES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_DMA_GET_CAPS: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_FB_GET_CAPS_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_GPU_GET_VIRTUALIZATION_MODE: ctrlHandler(rmControlSimple, compUtil),
0x80028b: ctrlHandler(rmControlSimple, compUtil), // unknown, paramsSize == 1
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_HOST_GET_CAPS_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00F8_CTRL_CMD_ATTACH_MEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00FD_CTRL_CMD_GET_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00FD_CTRL_CMD_ATTACH_MEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00FD_CTRL_CMD_DETACH_MEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_C2C_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_CE_GET_ALL_CAPS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_NAME_STRING: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_GID_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINES_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_PIDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_PID_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_CAPS_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_GPC_MASK: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_TPC_MASK: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GSP_GET_FEATURES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_MC_GET_ARCH_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_PERF_BOOST: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_HOST_GET_CAPS_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0080_CTRL_CMD_BSP_GET_CAPS_V2: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV00F8_CTRL_CMD_ATTACH_MEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00FD_CTRL_CMD_GET_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00FD_CTRL_CMD_ATTACH_MEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV00FD_CTRL_CMD_DETACH_MEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCI_BAR_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_BUS_GET_C2C_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_CE_GET_CAPS_V2: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_CE_GET_ALL_CAPS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFO_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_NAME_STRING: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ID: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_GPU_GET_GID_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_INFOROM_ECC_SUPPORT: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINES_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ACTIVE_PARTITION_IDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_PIDS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_PID_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_ZCULL_INFO: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_CAPS_V2: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_GPC_MASK: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_TPC_MASK: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GRMGR_GET_GR_FS_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_GSP_GET_FEATURES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_MC_GET_ARCH_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_MC_SERVICE_INTERRUPTS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_PERF_BOOST: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_TIMER_GET_TIME: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ: ctrlHandler(rmControlSimple, compUtil),
0x20810107: ctrlHandler(rmControlSimple, nvconf.CapGraphics), // unknown, paramsSize == TODO(ayushranjan)
nvgpu.NV503C_CTRL_CMD_REGISTER_VIDMEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV503C_CTRL_CMD_UNREGISTER_VIDMEM: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV83DE_CTRL_CMD_DEBUG_SET_EXCEPTION_MASK: ctrlHandler(rmControlSimple, compUtil),
@@ -307,9 +331,12 @@ func Init() {
nvgpu.NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV906F_CTRL_GET_CLASS_ENGINEID: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV906F_CTRL_CMD_RESET_CHANNEL: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NVC36F_CTRL_GET_CLASS_ENGINEID: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS: ctrlHandler(rmControlSimple, compUtil),
@@ -317,20 +344,28 @@ func Init() {
nvgpu.NVA06C_CTRL_CMD_SET_TIMESLICE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NVA06C_CTRL_CMD_PREEMPT: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NVA06F_CTRL_CMD_GPFIFO_SCHEDULE: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NVA06F_CTRL_CMD_BIND: ctrlHandler(rmControlSimple, nvconf.CapGraphics),
nvgpu.NVC56F_CTRL_CMD_GET_KMB: ctrlHandler(rmControlSimple, compUtil),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO: ctrlHandler(ctrlGpuGetIDInfo, compUtil),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION: ctrlHandler(ctrlClientSystemGetBuildVersion, compUtil),
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: ctrlHandler(ctrlGetNvU32List, compUtil),
nvgpu.NV0080_CTRL_CMD_GR_GET_CAPS: ctrlHandler(ctrlDevGetCaps, nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_GR_GET_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NvxxxCtrlXxxGetInfoParams], nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_FB_GET_CAPS: ctrlHandler(ctrlDevGetCaps, nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CAPS: ctrlHandler(ctrlDevGetCaps, nvconf.CapGraphics),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: ctrlHandler(ctrlDevFIFOGetChannelList, compUtil),
nvgpu.NV0080_CTRL_CMD_MSENC_GET_CAPS: ctrlHandler(ctrlDevGetCaps, nvconf.CapGraphics),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS: ctrlHandler(ctrlClientSystemGetP2PCaps, compUtil),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD: ctrlHandler(ctrlHasFrontendFD[nvgpu.NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS], compUtil),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD: ctrlHandler(ctrlHasFrontendFD[nvgpu.NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS], compUtil),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO: ctrlHandler(ctrlHasFrontendFD[nvgpu.NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS], compUtil),
nvgpu.NV0041_CTRL_CMD_GET_SURFACE_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NV0041_CTRL_GET_SURFACE_INFO_PARAMS], compUtil),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: ctrlHandler(ctrlDevFIFOGetChannelList, compUtil),
nvgpu.NV0041_CTRL_CMD_GET_SURFACE_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NvxxxCtrlXxxGetInfoParams], compUtil),
nvgpu.NV00FD_CTRL_CMD_ATTACH_GPU: ctrlHandler(ctrlMemoryMulticastFabricAttachGPU, compUtil),
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: ctrlHandler(ctrlDevGpuGetClasslist, compUtil),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINES: ctrlHandler(ctrlGetNvU32List, nvconf.CapGraphics),
nvgpu.NV2080_CTRL_CMD_BIOS_GET_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NvxxxCtrlXxxGetInfoParams], compUtil),
nvgpu.NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS: ctrlHandler(ctrlSubdevFIFODisableChannels, compUtil),
nvgpu.NV2080_CTRL_CMD_BIOS_GET_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NV2080_CTRL_BIOS_GET_INFO_PARAMS], compUtil),
nvgpu.NV2080_CTRL_CMD_GR_GET_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NV2080_CTRL_GR_GET_INFO_PARAMS], compUtil),
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO: ctrlHandler(ctrlIoctlHasInfoList[nvgpu.NvxxxCtrlXxxGetInfoParams], nvconf.CapGraphics),
nvgpu.NV503C_CTRL_CMD_REGISTER_VA_SPACE: ctrlHandler(ctrlRegisterVASpace, compUtil),
},
allocationClass: map[nvgpu.ClassID]allocationClassHandler{
@@ -340,23 +375,30 @@ func Init() {
nvgpu.NV01_MEMORY_LOCAL_USER: allocHandler(rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], compUtil),
nvgpu.NV01_ROOT_CLIENT: allocHandler(rmAllocRootClient, compUtil),
nvgpu.NV01_EVENT_OS_EVENT: allocHandler(rmAllocEventOSEvent, compUtil),
nvgpu.NV2081_BINAPI: allocHandler(rmAllocSimple[nvgpu.NV2081_ALLOC_PARAMETERS], compUtil),
nvgpu.NV01_MEMORY_VIRTUAL: allocHandler(rmAllocMemoryVirtual, nvconf.CapGraphics),
nvgpu.NV01_DEVICE_0: allocHandler(rmAllocSimple[nvgpu.NV0080_ALLOC_PARAMETERS], compUtil),
nvgpu.RM_USER_SHARED_DATA: allocHandler(rmAllocSimple[nvgpu.NV00DE_ALLOC_PARAMETERS], compUtil),
nvgpu.NV_MEMORY_FABRIC: allocHandler(rmAllocSimple[nvgpu.NV00F8_ALLOCATION_PARAMETERS], compUtil),
nvgpu.NV_MEMORY_MULTICAST_FABRIC: allocHandler(rmAllocSimple[nvgpu.NV00FD_ALLOCATION_PARAMETERS], compUtil),
nvgpu.NV20_SUBDEVICE_0: allocHandler(rmAllocSimple[nvgpu.NV2080_ALLOC_PARAMETERS], compUtil),
nvgpu.NV2081_BINAPI: allocHandler(rmAllocSimple[nvgpu.NV2081_ALLOC_PARAMETERS], compUtil),
nvgpu.NV50_MEMORY_VIRTUAL: allocHandler(rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], compUtil),
nvgpu.NV50_P2P: allocHandler(rmAllocSimple[nvgpu.NV503B_ALLOC_PARAMETERS], compUtil),
nvgpu.NV50_THIRD_PARTY_P2P: allocHandler(rmAllocSimple[nvgpu.NV503C_ALLOC_PARAMETERS], compUtil),
nvgpu.GF100_PROFILER: allocHandler(rmAllocNoParams, compUtil),
nvgpu.GT200_DEBUGGER: allocHandler(rmAllocSMDebuggerSession, compUtil),
nvgpu.FERMI_TWOD_A: allocHandler(rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], nvconf.CapGraphics),
nvgpu.FERMI_CONTEXT_SHARE_A: allocHandler(rmAllocContextShare, compUtil),
nvgpu.GF100_DISP_SW: allocHandler(rmAllocSimple[nvgpu.NV9072_ALLOCATION_PARAMETERS], nvconf.CapGraphics),
nvgpu.GF100_ZBC_CLEAR: allocHandler(rmAllocNoParams, nvconf.CapGraphics),
nvgpu.FERMI_VASPACE_A: allocHandler(rmAllocSimple[nvgpu.NV_VASPACE_ALLOCATION_PARAMETERS], compUtil),
nvgpu.KEPLER_CHANNEL_GROUP_A: allocHandler(rmAllocChannelGroup, compUtil),
nvgpu.KEPLER_INLINE_TO_MEMORY_B: allocHandler(rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], nvconf.CapGraphics),
nvgpu.VOLTA_USERMODE_A: allocHandler(rmAllocNoParams, nvconf.CapGraphics),
nvgpu.TURING_CHANNEL_GPFIFO_A: allocHandler(rmAllocChannel, compUtil),
nvgpu.AMPERE_CHANNEL_GPFIFO_A: allocHandler(rmAllocChannel, compUtil),
nvgpu.HOPPER_CHANNEL_GPFIFO_A: allocHandler(rmAllocChannel, compUtil),
nvgpu.TURING_A: allocHandler(rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], nvconf.CapGraphics),
nvgpu.TURING_DMA_COPY_A: allocHandler(rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], compUtil),
nvgpu.AMPERE_DMA_COPY_A: allocHandler(rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], compUtil),
nvgpu.AMPERE_DMA_COPY_B: allocHandler(rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], compUtil),
@@ -383,6 +425,9 @@ func Init() {
nvgpu.NV_ESC_RM_DUP_OBJECT: getStructName(nvgpu.NVOS55Parameters{}),
nvgpu.NV_ESC_RM_SHARE: getStructName(nvgpu.NVOS57Parameters{}),
nvgpu.NV_ESC_RM_UNMAP_MEMORY: getStructName(nvgpu.NVOS34Parameters{}),
nvgpu.NV_ESC_RM_ALLOC_CONTEXT_DMA2: getStructName(nvgpu.NVOS39Parameters{}),
nvgpu.NV_ESC_RM_MAP_MEMORY_DMA: getStructName(nvgpu.NVOS46Parameters{}),
nvgpu.NV_ESC_RM_UNMAP_MEMORY_DMA: getStructName(nvgpu.NVOS47Parameters{}),
nvgpu.NV_ESC_RM_UPDATE_DEVICE_MAPPING_INFO: getStructName(nvgpu.NVOS56Parameters{}),
nvgpu.NV_ESC_REGISTER_FD: getStructName(nvgpu.IoctlRegisterFD{}),
nvgpu.NV_ESC_ALLOC_OS_EVENT: getStructName(nvgpu.IoctlAllocOSEvent{}),
@@ -392,6 +437,7 @@ func Init() {
nvgpu.NV_ESC_RM_FREE: getStructName(nvgpu.NVOS00Parameters{}),
nvgpu.NV_ESC_RM_CONTROL: getStructName(nvgpu.NVOS54Parameters{}),
nvgpu.NV_ESC_RM_ALLOC: append(getStructName(nvgpu.NVOS21Parameters{}), getStructName(nvgpu.NVOS64Parameters{})...),
nvgpu.NV_ESC_RM_IDLE_CHANNELS: getStructName(nvgpu.NVOS30Parameters{}),
nvgpu.NV_ESC_RM_VID_HEAP_CONTROL: getStructName(nvgpu.NVOS32Parameters{}),
nvgpu.NV_ESC_RM_MAP_MEMORY: getStructName(nvgpu.IoctlNVOS33ParametersWithFD{}),
},
@@ -429,18 +475,24 @@ func Init() {
nvgpu.NV0000_CTRL_CMD_CLIENT_GET_ADDR_SPACE_TYPE: simpleIoctl("NV0000_CTRL_CLIENT_GET_ADDR_SPACE_TYPE_PARAMS"),
nvgpu.NV0000_CTRL_CMD_CLIENT_SET_INHERITED_SHARE_POLICY: simpleIoctl("NV0000_CTRL_CLIENT_SET_INHERITED_SHARE_POLICY_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ATTACHED_IDS: simpleIoctl("NV0000_CTRL_GPU_GET_ATTACHED_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_DEVICE_IDS: simpleIoctl("NV0000_CTRL_GPU_GET_DEVICE_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO_V2: simpleIoctl("NV0000_CTRL_GPU_GET_ID_INFO_V2_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_PROBED_IDS: simpleIoctl("NV0000_CTRL_GPU_GET_PROBED_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_ATTACH_IDS: simpleIoctl("NV0000_CTRL_GPU_ATTACH_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_DETACH_IDS: simpleIoctl("NV0000_CTRL_GPU_DETACH_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_PCI_INFO: simpleIoctl("NV0000_CTRL_GPU_GET_PCI_INFO_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_UUID_FROM_GPU_ID: simpleIoctl("NV0000_CTRL_GPU_GET_UUID_FROM_GPU_ID_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_QUERY_DRAIN_STATE: simpleIoctl("NV0000_CTRL_GPU_QUERY_DRAIN_STATE_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_MEMOP_ENABLE: simpleIoctl("NV0000_CTRL_GPU_GET_MEMOP_ENABLE_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GSYNC_GET_ATTACHED_IDS: simpleIoctl("NV0000_CTRL_GSYNC_GET_ATTACHED_IDS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYNC_GPU_BOOST_GROUP_INFO: simpleIoctl("NV0000_SYNC_GPU_BOOST_GROUP_INFO_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_CPU_INFO: simpleIoctl("NV0000_CTRL_SYSTEM_GET_CPU_INFO_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_V2: simpleIoctl("NV0000_CTRL_SYSTEM_GET_P2P_CAPS_V2_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_FABRIC_STATUS: simpleIoctl("NV0000_CTRL_SYSTEM_GET_FABRIC_STATUS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS_MATRIX: simpleIoctl("NV0000_CTRL_SYSTEM_GET_P2P_CAPS_MATRIX_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_FEATURES: simpleIoctl("NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS"),
nvgpu.NV0080_CTRL_CMD_DMA_ADV_SCHED_GET_VA_CAPS: simpleIoctl("NV0080_CTRL_DMA_ADV_SCHED_GET_VA_CAPS_PARAMS"),
nvgpu.NV0080_CTRL_CMD_DMA_GET_CAPS: simpleIoctl("NV0080_CTRL_DMA_GET_CAPS_PARAMS"),
nvgpu.NV0080_CTRL_CMD_FB_GET_CAPS_V2: simpleIoctl("NV0080_CTRL_FB_GET_CAPS_V2_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GPU_GET_NUM_SUBDEVICES: simpleIoctl("NV0080_CTRL_GPU_GET_NUM_SUBDEVICES_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GPU_QUERY_SW_STATE_PERSISTENCE: simpleIoctl("NV0080_CTRL_GPU_QUERY_SW_STATE_PERSISTENCE_PARAMS"),
@@ -448,6 +500,8 @@ func Init() {
0x80028b: nil, // unknown, paramsSize == 1
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST_V2: simpleIoctl("NV0080_CTRL_GPU_GET_CLASSLIST_V2_PARAMS"),
nvgpu.NV0080_CTRL_CMD_HOST_GET_CAPS_V2: simpleIoctl("NV0080_CTRL_HOST_GET_CAPS_V2_PARAMS"),
nvgpu.NV0080_CTRL_CMD_BSP_GET_CAPS_V2: simpleIoctl("NV0080_CTRL_BSP_GET_CAPS_PARAMS_V2"),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_ENGINE_CONTEXT_PROPERTIES: simpleIoctl("NV0080_CTRL_FIFO_GET_ENGINE_CONTEXT_PROPERTIES_PARAMS"),
nvgpu.NV00F8_CTRL_CMD_ATTACH_MEM: simpleIoctl("NV00F8_CTRL_ATTACH_MEM_PARAMS"),
nvgpu.NV00FD_CTRL_CMD_GET_INFO: simpleIoctl("NV00FD_CTRL_GET_INFO_PARAMS"),
nvgpu.NV00FD_CTRL_CMD_ATTACH_MEM: simpleIoctl("NV00FD_CTRL_ATTACH_MEM_PARAMS"),
@@ -457,9 +511,15 @@ func Init() {
nvgpu.NV2080_CTRL_CMD_BUS_GET_INFO_V2: simpleIoctl("NV2080_CTRL_BUS_GET_INFO_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS: simpleIoctl("NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BUS_GET_C2C_INFO: simpleIoctl("NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK: simpleIoctl("NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS"),
nvgpu.NV2080_CTRL_CMD_CE_GET_CAPS_V2: simpleIoctl("NV2080_CTRL_CE_GET_CAPS_V2_PARAMS"),
0x20810107: nil, // unknown, paramsSize == TODO(ayushranjan)
nvgpu.NV2080_CTRL_CMD_CE_GET_ALL_CAPS: simpleIoctl("NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION: simpleIoctl("NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO_V2: simpleIoctl("NV2080_CTRL_FB_GET_INFO_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FB_GET_GPU_CACHE_INFO: simpleIoctl("NV2080_CTRL_FB_GET_GPU_CACHE_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO: simpleIoctl("NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FB_GET_SEMAPHORE_SURFACE_LAYOUT: simpleIoctl("NV2080_CTRL_FB_GET_SEMAPHORE_SURFACE_LAYOUT_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFO_V2: simpleIoctl("NV2080_CTRL_GPU_GET_INFO_V2_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE: simpleIoctl("NV2080_CTRL_FLCN_GET_CTX_BUFFER_SIZE_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_NAME_STRING: simpleIoctl("NV2080_CTRL_GPU_GET_NAME_STRING_PARAMS"),
@@ -467,10 +527,12 @@ func Init() {
nvgpu.NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_SIMULATION_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS: simpleIoctl("NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_COMPUTE_MODE_RULES: simpleIoctl("NV2080_CTRL_GPU_QUERY_COMPUTE_MODE_RULES_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ID: simpleIoctl("NV2080_CTRL_GPU_GET_ID_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_QUERY_ECC_CONFIGURATION: simpleIoctl("NV2080_CTRL_GPU_QUERY_ECC_CONFIGURATION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_OEM_BOARD_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_ACQUIRE_COMPUTE_MODE_RESERVATION: nil, // undocumented; paramSize == 0
nvgpu.NV2080_CTRL_CMD_GPU_RELEASE_COMPUTE_MODE_RESERVATION: nil, // undocumented; paramSize == 0
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINE_PARTNERLIST: simpleIoctl("NV2080_CTRL_GPU_GET_ENGINE_PARTNERLIST_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_GID_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_GID_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_OBJECT_VERSION: simpleIoctl("NV2080_CTRL_GPU_GET_INFOROM_OBJECT_VERSION_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION: simpleIoctl("NV2080_CTRL_GPU_GET_INFOROM_IMAGE_VERSION_PARAMS"),
@@ -481,6 +543,8 @@ func Init() {
nvgpu.NV2080_CTRL_CMD_GPU_GET_PID_INFO: simpleIoctl("NV2080_CTRL_GPU_GET_PID_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GPU_GET_COMPUTE_POLICY_CONFIG: simpleIoctl("NV2080_CTRL_GPU_GET_COMPUTE_POLICY_CONFIG_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO: simpleIoctl("NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_ZCULL_INFO: simpleIoctl("NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND: simpleIoctl("NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE: simpleIoctl("NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_CTX_BUFFER_SIZE: simpleIoctl("NV2080_CTRL_GR_GET_CTX_BUFFER_SIZE_PARAMS"),
nvgpu.NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER: simpleIoctl("NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS"),
@@ -498,6 +562,7 @@ func Init() {
nvgpu.NV2080_CTRL_CMD_RC_GET_WATCHDOG_INFO: simpleIoctl("NV2080_CTRL_RC_GET_WATCHDOG_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_RC_RELEASE_WATCHDOG_REQUESTS: nil, // No params.
nvgpu.NV2080_CTRL_CMD_RC_SOFT_DISABLE_WATCHDOG: nil, // No params.
nvgpu.NV2080_CTRL_CMD_TIMER_GET_TIME: simpleIoctl("NV2080_CTRL_TIMER_GET_TIME_PARAMS"),
nvgpu.NV2080_CTRL_CMD_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO: simpleIoctl("NV2080_CTRL_TIMER_GET_GPU_CPU_TIME_CORRELATION_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ: simpleIoctl("NV2080_CTRL_CMD_TIMER_SET_GR_TICK_FREQ_PARAMS"),
nvgpu.NV503C_CTRL_CMD_REGISTER_VIDMEM: simpleIoctl("NV503C_CTRL_REGISTER_VIDMEM_PARAMS"),
@@ -507,9 +572,12 @@ func Init() {
nvgpu.NV83DE_CTRL_CMD_DEBUG_CLEAR_ALL_SM_ERROR_STATES: simpleIoctl("NV83DE_CTRL_DEBUG_CLEAR_ALL_SM_ERROR_STATES_PARAMS"),
nvgpu.NV906F_CTRL_GET_CLASS_ENGINEID: simpleIoctl("NV906F_CTRL_GET_CLASS_ENGINEID_PARAMS"),
nvgpu.NV906F_CTRL_CMD_RESET_CHANNEL: simpleIoctl("NV906F_CTRL_CMD_RESET_CHANNEL_PARAMS"),
nvgpu.NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_SIZE: simpleIoctl("NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS"),
nvgpu.NV9096_CTRL_CMD_GET_ZBC_CLEAR_TABLE_ENTRY: simpleIoctl("NV9096_CTRL_GET_ZBC_CLEAR_TABLE_ENTRY_PARAMS"),
nvgpu.NV90E6_CTRL_CMD_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK: simpleIoctl("NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS"),
nvgpu.NVC36F_CTRL_GET_CLASS_ENGINEID: simpleIoctl("NVC36F_CTRL_GET_CLASS_ENGINEID_PARAMS"),
nvgpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: simpleIoctl("NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN_PARAMS"),
nvgpu.NVC36F_CTRL_CMD_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX: simpleIoctl("NVC36F_CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX_PARAMS"),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES: simpleIoctl("NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES_PARAMS"),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE: simpleIoctl("NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE_PARAMS"),
nvgpu.NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS: simpleIoctl("NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS"),
@@ -517,20 +585,28 @@ func Init() {
nvgpu.NVA06C_CTRL_CMD_SET_TIMESLICE: simpleIoctl("NVA06C_CTRL_SET_TIMESLICE_PARAMS"),
nvgpu.NVA06C_CTRL_CMD_PREEMPT: simpleIoctl("NVA06C_CTRL_PREEMPT_PARAMS"),
nvgpu.NVA06F_CTRL_CMD_GPFIFO_SCHEDULE: simpleIoctl("NVA06F_CTRL_GPFIFO_SCHEDULE_PARAMS"),
nvgpu.NVA06F_CTRL_CMD_BIND: simpleIoctl("NVA06F_CTRL_BIND_PARAMS"),
nvgpu.NVC56F_CTRL_CMD_GET_KMB: simpleIoctl("NVC56F_CTRL_CMD_GET_KMB_PARAMS"),
nvgpu.NV0000_CTRL_CMD_GPU_GET_ID_INFO: getStructName(nvgpu.NV0000_CTRL_GPU_GET_ID_INFO_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION: getStructName(nvgpu.NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS{}),
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: driverStructWith(nvgpu.RmapiParamNvU32List{}, "NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GR_GET_CAPS: driverStructWith(nvgpu.NV0080_CTRL_GET_CAPS_PARAMS{}, "NV0080_CTRL_GR_GET_CAPS_PARAMS"),
nvgpu.NV0080_CTRL_CMD_GR_GET_INFO: driverStructWith(nvgpu.NvxxxCtrlXxxGetInfoParams{}, "NV0080_CTRL_GR_GET_INFO_PARAMS"),
nvgpu.NV0080_CTRL_CMD_FB_GET_CAPS: driverStructWith(nvgpu.NV0080_CTRL_GET_CAPS_PARAMS{}, "NV0080_CTRL_FB_GET_CAPS_PARAMS"),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CAPS: driverStructWith(nvgpu.NV0080_CTRL_GET_CAPS_PARAMS{}, "NV0080_CTRL_FIFO_GET_CAPS_PARAMS"),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: getStructName(nvgpu.NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS{}),
nvgpu.NV0080_CTRL_CMD_MSENC_GET_CAPS: driverStructWith(nvgpu.NV0080_CTRL_GET_CAPS_PARAMS{}, "NV0080_CTRL_MSENC_GET_CAPS_PARAMS"),
nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_P2P_CAPS: getStructName(nvgpu.NV0000_CTRL_SYSTEM_GET_P2P_CAPS_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_EXPORT_OBJECT_TO_FD: getStructName(nvgpu.NV0000_CTRL_OS_UNIX_EXPORT_OBJECT_TO_FD_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_IMPORT_OBJECT_FROM_FD: getStructName(nvgpu.NV0000_CTRL_OS_UNIX_IMPORT_OBJECT_FROM_FD_PARAMS{}),
nvgpu.NV0000_CTRL_CMD_OS_UNIX_GET_EXPORT_OBJECT_INFO: getStructName(nvgpu.NV0000_CTRL_OS_UNIX_GET_EXPORT_OBJECT_INFO_PARAMS{}),
nvgpu.NV0041_CTRL_CMD_GET_SURFACE_INFO: getStructName(nvgpu.NV0041_CTRL_GET_SURFACE_INFO_PARAMS{}),
nvgpu.NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: getStructName(nvgpu.NV0080_CTRL_FIFO_GET_CHANNELLIST_PARAMS{}),
nvgpu.NV0041_CTRL_CMD_GET_SURFACE_INFO: driverStructWith(nvgpu.NvxxxCtrlXxxGetInfoParams{}, "NV0041_CTRL_GET_SURFACE_INFO_PARAMS"),
nvgpu.NV00FD_CTRL_CMD_ATTACH_GPU: getStructName(nvgpu.NV00FD_CTRL_ATTACH_GPU_PARAMS{}),
nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: getStructName(nvgpu.NV0080_CTRL_GPU_GET_CLASSLIST_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_GPU_GET_ENGINES: driverStructWith(nvgpu.RmapiParamNvU32List{}, "NV2080_CTRL_GPU_GET_ENGINES_PARAMS"),
nvgpu.NV2080_CTRL_CMD_BIOS_GET_INFO: driverStructWith(nvgpu.NvxxxCtrlXxxGetInfoParams{}, "NV2080_CTRL_BIOS_GET_INFO_PARAMS"),
nvgpu.NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS: getStructName(nvgpu.NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_BIOS_GET_INFO: getStructName(nvgpu.NV2080_CTRL_BIOS_GET_INFO_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_GR_GET_INFO: getStructName(nvgpu.NV2080_CTRL_GR_GET_INFO_PARAMS{}),
nvgpu.NV2080_CTRL_CMD_FB_GET_INFO: driverStructWith(nvgpu.NvxxxCtrlXxxGetInfoParams{}, "NV2080_CTRL_FB_GET_INFO_PARAMS"),
nvgpu.NV503C_CTRL_CMD_REGISTER_VA_SPACE: getStructName(nvgpu.NV503C_CTRL_REGISTER_VA_SPACE_PARAMS{}),
},
allocationNames: map[nvgpu.ClassID][]DriverStruct{
@@ -540,23 +616,30 @@ func Init() {
nvgpu.NV01_MEMORY_LOCAL_USER: getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS{}),
nvgpu.NV01_ROOT_CLIENT: getStructName(nvgpu.Handle{}),
nvgpu.NV01_EVENT_OS_EVENT: getStructName(nvgpu.NV0005_ALLOC_PARAMETERS{}),
nvgpu.NV2081_BINAPI: getStructName(nvgpu.NV2081_ALLOC_PARAMETERS{}),
nvgpu.NV01_MEMORY_VIRTUAL: getStructName(nvgpu.NV_MEMORY_VIRTUAL_ALLOCATION_PARAMS{}),
nvgpu.NV01_DEVICE_0: getStructName(nvgpu.NV0080_ALLOC_PARAMETERS{}),
nvgpu.RM_USER_SHARED_DATA: getStructName(nvgpu.NV00DE_ALLOC_PARAMETERS{}),
nvgpu.NV_MEMORY_FABRIC: getStructName(nvgpu.NV00F8_ALLOCATION_PARAMETERS{}),
nvgpu.NV_MEMORY_MULTICAST_FABRIC: getStructName(nvgpu.NV00FD_ALLOCATION_PARAMETERS{}),
nvgpu.NV20_SUBDEVICE_0: getStructName(nvgpu.NV2080_ALLOC_PARAMETERS{}),
nvgpu.NV2081_BINAPI: getStructName(nvgpu.NV2081_ALLOC_PARAMETERS{}),
nvgpu.NV50_MEMORY_VIRTUAL: getStructName(nvgpu.NV_MEMORY_ALLOCATION_PARAMS{}),
nvgpu.NV50_P2P: getStructName(nvgpu.NV503B_ALLOC_PARAMETERS{}),
nvgpu.NV50_THIRD_PARTY_P2P: getStructName(nvgpu.NV503C_ALLOC_PARAMETERS{}),
nvgpu.GT200_DEBUGGER: getStructName(nvgpu.NV83DE_ALLOC_PARAMETERS{}),
nvgpu.GF100_PROFILER: nil, // No params
nvgpu.FERMI_TWOD_A: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.FERMI_CONTEXT_SHARE_A: getStructName(nvgpu.NV_CTXSHARE_ALLOCATION_PARAMETERS{}),
nvgpu.GF100_DISP_SW: getStructName(nvgpu.NV9072_ALLOCATION_PARAMETERS{}),
nvgpu.GF100_ZBC_CLEAR: nil, // No params
nvgpu.FERMI_VASPACE_A: getStructName(nvgpu.NV_VASPACE_ALLOCATION_PARAMETERS{}),
nvgpu.KEPLER_CHANNEL_GROUP_A: getStructName(nvgpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS{}),
nvgpu.KEPLER_INLINE_TO_MEMORY_B: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.VOLTA_USERMODE_A: nil, // No params
nvgpu.TURING_CHANNEL_GPFIFO_A: getStructName(nvgpu.NV_CHANNEL_ALLOC_PARAMS{}),
nvgpu.AMPERE_CHANNEL_GPFIFO_A: getStructName(nvgpu.NV_CHANNEL_ALLOC_PARAMS{}),
nvgpu.HOPPER_CHANNEL_GPFIFO_A: getStructName(nvgpu.NV_CHANNEL_ALLOC_PARAMS{}),
nvgpu.TURING_A: getStructName(nvgpu.NV_GR_ALLOCATION_PARAMETERS{}),
nvgpu.TURING_DMA_COPY_A: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
nvgpu.AMPERE_DMA_COPY_A: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
nvgpu.AMPERE_DMA_COPY_B: getStructName(nvgpu.NVB0B5_ALLOCATION_PARAMETERS{}),
@@ -631,6 +714,7 @@ func Init() {
abi.getStructNames = func() *driverStructNames {
names := prevNames()
names.frontendNames[nvgpu.NV_ESC_WAIT_OPEN_COMPLETE] = getStructName(nvgpu.IoctlWaitOpenComplete{})
names.frontendNames[nvgpu.NV_ESC_RM_UNMAP_MEMORY_DMA] = getStructName(nvgpu.NVOS47ParametersV550{})
names.controlNames[nvgpu.NV0000_CTRL_CMD_GPU_ASYNC_ATTACH_ID] = simpleIoctl("NV0000_CTRL_GPU_ASYNC_ATTACH_ID_PARAMS")
names.controlNames[nvgpu.NV0000_CTRL_CMD_GPU_WAIT_ATTACH_ID] = simpleIoctl("NV0000_CTRL_GPU_WAIT_ATTACH_ID_PARAMS")
names.controlNames[nvgpu.NV0080_CTRL_CMD_PERF_CUDA_LIMIT_SET_CONTROL] = simpleIoctl("NV0080_CTRL_PERF_CUDA_LIMIT_CONTROL_PARAMS")
@@ -767,6 +851,22 @@ func getStructName(params any) []DriverStruct {
}
}
func driverStructWith(params any, driverName string) []DriverStruct {
paramType := reflect.TypeOf(params)
// Right now, we only expect parameter structs
if paramType.Kind() != reflect.Struct {
panic(fmt.Sprintf("expected struct, got %v", paramType.Kind()))
}
return []DriverStruct{
{
Name: driverName,
Type: paramType,
},
}
}
// ForEachSupportDriver calls f on all supported drivers.
// Precondition: Init() must have been called.
func ForEachSupportDriver(f func(version DriverVersion, checksum string)) {