diff --git a/pkg/abi/nvgpu/classes.go b/pkg/abi/nvgpu/classes.go index 99c30b4ad..7077e4570 100644 --- a/pkg/abi/nvgpu/classes.go +++ b/pkg/abi/nvgpu/classes.go @@ -45,9 +45,11 @@ const ( AMPERE_COMPUTE_A = 0x0000c6c0 AMPERE_DMA_COPY_B = 0x0000c7b5 AMPERE_COMPUTE_B = 0x0000c7c0 + HOPPER_CHANNEL_GPFIFO_A = 0x0000c86f HOPPER_DMA_COPY_A = 0x0000c8b5 ADA_COMPUTE_A = 0x0000c9c0 NV_CONFIDENTIAL_COMPUTE = 0x0000cb33 + HOPPER_SEC2_WORK_LAUNCH_A = 0x0000cba2 HOPPER_COMPUTE_A = 0x0000cbc0 ) diff --git a/pkg/abi/nvgpu/ctrl.go b/pkg/abi/nvgpu/ctrl.go index 52530f5e3..3c2adf241 100644 --- a/pkg/abi/nvgpu/ctrl.go +++ b/pkg/abi/nvgpu/ctrl.go @@ -160,6 +160,11 @@ const ( NV2080_CTRL_FIFO_DISABLE_CHANNELS_MAX_ENTRIES = 64 ) +// From src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h: +const ( + NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE = 0x20803125 +) + // +marshal type NV2080_CTRL_FIFO_DISABLE_CHANNELS_PARAMS struct { BDisable uint8 @@ -266,6 +271,11 @@ const ( NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN = 0xc36f0108 ) +// From src/common/sdk/nvidia/inc/ctrl/ctrlc56f.h: +const ( + NVC56F_CTRL_CMD_GET_KMB = 0xc56f010b +) + // From src/common/sdk/nvidia/inc/ctrl/ctrl906f.h: const ( NV906F_CTRL_CMD_RESET_CHANNEL = 0x906f0102 @@ -290,5 +300,7 @@ const ( // From src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h: const ( - NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101 + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES = 0xcb330101 + NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE = 0xcb330104 + NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS = 0xcb33010b ) diff --git a/pkg/abi/nvgpu/nvgpu.go b/pkg/abi/nvgpu/nvgpu.go index 4a5a2da1d..4f2edfcef 100644 --- a/pkg/abi/nvgpu/nvgpu.go +++ b/pkg/abi/nvgpu/nvgpu.go @@ -68,3 +68,8 @@ type RS_SHARE_POLICY struct { Action uint8 Pad [1]byte } + +// NvUUID is defined in src/common/inc/nvCpuUuid.h. +// +// +marshal +type NvUUID [16]uint8 diff --git a/pkg/abi/nvgpu/uvm.go b/pkg/abi/nvgpu/uvm.go index 42ec1b670..f09f50ae0 100644 --- a/pkg/abi/nvgpu/uvm.go +++ b/pkg/abi/nvgpu/uvm.go @@ -40,6 +40,7 @@ const ( UVM_REGISTER_GPU = 37 UVM_UNREGISTER_GPU = 38 UVM_PAGEABLE_MEM_ACCESS = 39 + UVM_SET_PREFERRED_LOCATION = 42 UVM_DISABLE_READ_DUPLICATION = 45 UVM_MAP_DYNAMIC_PARALLELISM_REGION = 65 UVM_ALLOC_SEMAPHORE_POOL = 68 @@ -76,7 +77,7 @@ type UVM_DESTROY_RANGE_GROUP_PARAMS struct { // +marshal type UVM_REGISTER_GPU_VASPACE_PARAMS struct { - GPUUUID [16]uint8 + GPUUUID NvUUID RMCtrlFD int32 HClient Handle HVASpace Handle @@ -93,13 +94,13 @@ func (p *UVM_REGISTER_GPU_VASPACE_PARAMS) SetRMCtrlFD(fd int32) { // +marshal type UVM_UNREGISTER_GPU_VASPACE_PARAMS struct { - GPUUUID [16]uint8 + GPUUUID NvUUID RMStatus uint32 } // +marshal type UVM_REGISTER_CHANNEL_PARAMS struct { - GPUUUID [16]uint8 + GPUUUID NvUUID RMCtrlFD int32 HClient Handle HChannel Handle @@ -120,7 +121,7 @@ func (p *UVM_REGISTER_CHANNEL_PARAMS) SetRMCtrlFD(fd int32) { // +marshal type UVM_UNREGISTER_CHANNEL_PARAMS struct { - GPUUUID [16]uint8 + GPUUUID NvUUID HClient Handle HChannel Handle RMStatus uint32 @@ -178,7 +179,7 @@ type UVM_FREE_PARAMS struct { // +marshal type UVM_REGISTER_GPU_PARAMS struct { - GPUUUID [16]uint8 + GPUUUID NvUUID NumaEnabled uint8 Pad [3]byte NumaNodeID int32 @@ -198,7 +199,7 @@ func (p *UVM_REGISTER_GPU_PARAMS) SetRMCtrlFD(fd int32) { // +marshal type UVM_UNREGISTER_GPU_PARAMS struct { - GPUUUID [16]uint8 + GPUUUID NvUUID RMStatus uint32 } @@ -209,6 +210,24 @@ type UVM_PAGEABLE_MEM_ACCESS_PARAMS struct { RMStatus uint32 } +// +marshal +type UVM_SET_PREFERRED_LOCATION_PARAMS struct { + RequestedBase uint64 + Length uint64 + PreferredLocation NvUUID + RMStatus uint32 + Pad0 [4]byte +} + +// +marshal +type UVM_SET_PREFERRED_LOCATION_PARAMS_V550 struct { + RequestedBase uint64 + Length uint64 + PreferredLocation NvUUID + PreferredCPUNumaNode int32 + RMStatus uint32 +} + // +marshal type UVM_DISABLE_READ_DUPLICATION_PARAMS struct { RequestedBase uint64 @@ -221,7 +240,7 @@ type UVM_DISABLE_READ_DUPLICATION_PARAMS struct { type UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS struct { Base uint64 Length uint64 - GPUUUID [16]uint8 + GPUUUID NvUUID RMStatus uint32 Pad0 [4]byte } @@ -277,7 +296,7 @@ const ( // +marshal type UvmGpuMappingAttributes struct { - GPUUUID [16]byte + GPUUUID NvUUID GPUMappingType uint32 GPUCachingType uint32 GPUFormatType uint32 diff --git a/pkg/sentry/devices/nvproxy/seccomp_filters.go b/pkg/sentry/devices/nvproxy/seccomp_filters.go index d0ae550e6..c31a8620b 100644 --- a/pkg/sentry/devices/nvproxy/seccomp_filters.go +++ b/pkg/sentry/devices/nvproxy/seccomp_filters.go @@ -154,6 +154,10 @@ func Filters() seccomp.SyscallRules { seccomp.NonNegativeFD{}, seccomp.EqualTo(nvgpu.UVM_PAGEABLE_MEM_ACCESS), }, + seccomp.PerArg{ + seccomp.NonNegativeFD{}, + seccomp.EqualTo(nvgpu.UVM_SET_PREFERRED_LOCATION), + }, seccomp.PerArg{ seccomp.NonNegativeFD{}, seccomp.EqualTo(nvgpu.UVM_DISABLE_READ_DUPLICATION), diff --git a/pkg/sentry/devices/nvproxy/version.go b/pkg/sentry/devices/nvproxy/version.go index 2cff97585..a741234a3 100644 --- a/pkg/sentry/devices/nvproxy/version.go +++ b/pkg/sentry/devices/nvproxy/version.go @@ -187,6 +187,7 @@ func Init() { nvgpu.UVM_REGISTER_GPU: uvmIoctlHasRMCtrlFD[nvgpu.UVM_REGISTER_GPU_PARAMS], nvgpu.UVM_UNREGISTER_GPU: uvmIoctlSimple[nvgpu.UVM_UNREGISTER_GPU_PARAMS], nvgpu.UVM_PAGEABLE_MEM_ACCESS: uvmIoctlSimple[nvgpu.UVM_PAGEABLE_MEM_ACCESS_PARAMS], + nvgpu.UVM_SET_PREFERRED_LOCATION: uvmIoctlSimple[nvgpu.UVM_SET_PREFERRED_LOCATION_PARAMS], nvgpu.UVM_DISABLE_READ_DUPLICATION: uvmIoctlSimple[nvgpu.UVM_DISABLE_READ_DUPLICATION_PARAMS], nvgpu.UVM_MAP_DYNAMIC_PARALLELISM_REGION: uvmIoctlSimple[nvgpu.UVM_MAP_DYNAMIC_PARALLELISM_REGION_PARAMS], nvgpu.UVM_ALLOC_SEMAPHORE_POOL: uvmIoctlSimple[nvgpu.UVM_ALLOC_SEMAPHORE_POOL_PARAMS], @@ -226,6 +227,7 @@ func Init() { nvgpu.NV2080_CTRL_CMD_CE_GET_ALL_CAPS: rmControlSimple, nvgpu.NV2080_CTRL_CMD_FB_GET_INFO_V2: rmControlSimple, nvgpu.NV2080_CTRL_CMD_GPU_GET_INFO_V2: rmControlSimple, + nvgpu.NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_SIZE: rmControlSimple, nvgpu.NV2080_CTRL_CMD_GPU_GET_NAME_STRING: rmControlSimple, nvgpu.NV2080_CTRL_CMD_GPU_GET_SHORT_NAME_STRING: rmControlSimple, nvgpu.NV2080_CTRL_CMD_GPU_GET_SIMULATION_INFO: rmControlSimple, @@ -268,10 +270,13 @@ func Init() { nvgpu.NVC36F_CTRL_GET_CLASS_ENGINEID: rmControlSimple, nvgpu.NVC36F_CTRL_CMD_GPFIFO_GET_WORK_SUBMIT_TOKEN: rmControlSimple, nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_CAPABILITIES: rmControlSimple, + nvgpu.NV_CONF_COMPUTE_CTRL_CMD_SYSTEM_GET_GPUS_STATE: rmControlSimple, + nvgpu.NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS: rmControlSimple, nvgpu.NVA06C_CTRL_CMD_GPFIFO_SCHEDULE: rmControlSimple, nvgpu.NVA06C_CTRL_CMD_SET_TIMESLICE: rmControlSimple, nvgpu.NVA06C_CTRL_CMD_PREEMPT: rmControlSimple, nvgpu.NVA06F_CTRL_CMD_GPFIFO_SCHEDULE: rmControlSimple, + nvgpu.NVC56F_CTRL_CMD_GET_KMB: rmControlSimple, nvgpu.NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION: ctrlClientSystemGetBuildVersion, nvgpu.NV0080_CTRL_CMD_FIFO_GET_CHANNELLIST: ctrlDevFIFOGetChannelList, nvgpu.NV0080_CTRL_CMD_GPU_GET_CLASSLIST: ctrlDevGpuGetClasslist, @@ -279,38 +284,40 @@ func Init() { nvgpu.NV2080_CTRL_CMD_GR_GET_INFO: ctrlSubdevGRGetInfo, }, allocationClass: map[uint32]allocationClassHandler{ - nvgpu.NV01_ROOT: rmAllocSimple[nvgpu.Handle], - nvgpu.NV01_ROOT_NON_PRIV: rmAllocSimple[nvgpu.Handle], - nvgpu.NV01_MEMORY_SYSTEM: rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], - nvgpu.NV01_MEMORY_LOCAL_USER: rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], - nvgpu.NV01_ROOT_CLIENT: rmAllocSimple[nvgpu.Handle], - nvgpu.NV01_EVENT_OS_EVENT: rmAllocEventOSEvent, - nvgpu.NV2081_BINAPI: rmAllocSimple[nvgpu.NV2081_ALLOC_PARAMETERS], - nvgpu.NV01_DEVICE_0: rmAllocSimple[nvgpu.NV0080_ALLOC_PARAMETERS], - nvgpu.NV_MEMORY_FABRIC: rmAllocSimple[nvgpu.NV00F8_ALLOCATION_PARAMETERS], - nvgpu.NV20_SUBDEVICE_0: rmAllocSimple[nvgpu.NV2080_ALLOC_PARAMETERS], - nvgpu.NV50_MEMORY_VIRTUAL: rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], - nvgpu.NV50_P2P: rmAllocSimple[nvgpu.NV503B_ALLOC_PARAMETERS], - nvgpu.NV50_THIRD_PARTY_P2P: rmAllocSimple[nvgpu.NV503C_ALLOC_PARAMETERS], - nvgpu.GT200_DEBUGGER: rmAllocSimple[nvgpu.NV83DE_ALLOC_PARAMETERS], - nvgpu.FERMI_CONTEXT_SHARE_A: rmAllocSimple[nvgpu.NV_CTXSHARE_ALLOCATION_PARAMETERS], - nvgpu.FERMI_VASPACE_A: rmAllocSimple[nvgpu.NV_VASPACE_ALLOCATION_PARAMETERS], - nvgpu.KEPLER_CHANNEL_GROUP_A: rmAllocSimple[nvgpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS], - nvgpu.TURING_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS], - nvgpu.AMPERE_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS], - nvgpu.TURING_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], - nvgpu.AMPERE_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], - nvgpu.AMPERE_DMA_COPY_B: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], - nvgpu.HOPPER_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], - nvgpu.TURING_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], - nvgpu.AMPERE_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], - nvgpu.AMPERE_COMPUTE_B: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], - nvgpu.ADA_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], - nvgpu.NV_CONFIDENTIAL_COMPUTE: rmAllocSimple[nvgpu.NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS], - nvgpu.HOPPER_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], - nvgpu.HOPPER_USERMODE_A: rmAllocSimple[nvgpu.NV_HOPPER_USERMODE_A_PARAMS], - nvgpu.GF100_SUBDEVICE_MASTER: rmAllocNoParams, - nvgpu.TURING_USERMODE_A: rmAllocNoParams, + nvgpu.NV01_ROOT: rmAllocSimple[nvgpu.Handle], + nvgpu.NV01_ROOT_NON_PRIV: rmAllocSimple[nvgpu.Handle], + nvgpu.NV01_MEMORY_SYSTEM: rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], + nvgpu.NV01_MEMORY_LOCAL_USER: rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], + nvgpu.NV01_ROOT_CLIENT: rmAllocSimple[nvgpu.Handle], + nvgpu.NV01_EVENT_OS_EVENT: rmAllocEventOSEvent, + nvgpu.NV2081_BINAPI: rmAllocSimple[nvgpu.NV2081_ALLOC_PARAMETERS], + nvgpu.NV01_DEVICE_0: rmAllocSimple[nvgpu.NV0080_ALLOC_PARAMETERS], + nvgpu.NV_MEMORY_FABRIC: rmAllocSimple[nvgpu.NV00F8_ALLOCATION_PARAMETERS], + nvgpu.NV20_SUBDEVICE_0: rmAllocSimple[nvgpu.NV2080_ALLOC_PARAMETERS], + nvgpu.NV50_MEMORY_VIRTUAL: rmAllocSimple[nvgpu.NV_MEMORY_ALLOCATION_PARAMS], + nvgpu.NV50_P2P: rmAllocSimple[nvgpu.NV503B_ALLOC_PARAMETERS], + nvgpu.NV50_THIRD_PARTY_P2P: rmAllocSimple[nvgpu.NV503C_ALLOC_PARAMETERS], + nvgpu.GT200_DEBUGGER: rmAllocSimple[nvgpu.NV83DE_ALLOC_PARAMETERS], + nvgpu.FERMI_CONTEXT_SHARE_A: rmAllocSimple[nvgpu.NV_CTXSHARE_ALLOCATION_PARAMETERS], + nvgpu.FERMI_VASPACE_A: rmAllocSimple[nvgpu.NV_VASPACE_ALLOCATION_PARAMETERS], + nvgpu.KEPLER_CHANNEL_GROUP_A: rmAllocSimple[nvgpu.NV_CHANNEL_GROUP_ALLOCATION_PARAMETERS], + nvgpu.TURING_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS], + nvgpu.AMPERE_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS], + nvgpu.HOPPER_CHANNEL_GPFIFO_A: rmAllocSimple[nvgpu.NV_CHANNEL_ALLOC_PARAMS], + nvgpu.TURING_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], + nvgpu.AMPERE_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], + nvgpu.AMPERE_DMA_COPY_B: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], + nvgpu.HOPPER_DMA_COPY_A: rmAllocSimple[nvgpu.NVB0B5_ALLOCATION_PARAMETERS], + nvgpu.TURING_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], + nvgpu.AMPERE_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], + nvgpu.AMPERE_COMPUTE_B: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], + nvgpu.ADA_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], + nvgpu.NV_CONFIDENTIAL_COMPUTE: rmAllocSimple[nvgpu.NV_CONFIDENTIAL_COMPUTE_ALLOC_PARAMS], + nvgpu.HOPPER_COMPUTE_A: rmAllocSimple[nvgpu.NV_GR_ALLOCATION_PARAMETERS], + nvgpu.HOPPER_USERMODE_A: rmAllocSimple[nvgpu.NV_HOPPER_USERMODE_A_PARAMS], + nvgpu.GF100_SUBDEVICE_MASTER: rmAllocNoParams, + nvgpu.TURING_USERMODE_A: rmAllocNoParams, + nvgpu.HOPPER_SEC2_WORK_LAUNCH_A: rmAllocNoParams, }, } }) @@ -347,6 +354,7 @@ func Init() { // NV2081_BINAPI forwards all control commands to the GSP in // src/nvidia/src/kernel/rmapi/binary_api.c:binapiControl_IMPL(). abi.controlCmd[(nvgpu.NV2081_BINAPI<<16)|0x0108] = rmControlSimple + abi.uvmIoctl[nvgpu.UVM_SET_PREFERRED_LOCATION] = uvmIoctlSimple[nvgpu.UVM_SET_PREFERRED_LOCATION_PARAMS_V550] return abi }