From 8d98518e9d060daf188dfd33414ef7da44e12290 Mon Sep 17 00:00:00 2001 From: Andrei Vagin Date: Tue, 4 Apr 2023 20:22:02 -0700 Subject: [PATCH] test: check return codes of tgkill syscalls otherwise the compiler can drop inline assembly bits. PiperOrigin-RevId: 521936364 --- test/syscalls/linux/fpsig_fork.cc | 32 +++++-------- test/syscalls/linux/fpsig_nested.cc | 66 +++++++++++--------------- test/syscalls/linux/sigreturn_arm64.cc | 3 +- 3 files changed, 43 insertions(+), 58 deletions(-) diff --git a/test/syscalls/linux/fpsig_fork.cc b/test/syscalls/linux/fpsig_fork.cc index d786b2c20..ae03fe3ba 100644 --- a/test/syscalls/linux/fpsig_fork.cc +++ b/test/syscalls/linux/fpsig_fork.cc @@ -95,28 +95,22 @@ TEST(FPSigTest, Fork) { uint64_t expected = 0xdeadbeeffacefeed; SET_FP0(expected); + int64_t ret; #ifdef __x86_64__ - asm volatile( - "movl %[killnr], %%eax;" - "movl %[parent], %%edi;" - "movl %[tid], %%esi;" - "movl %[sig], %%edx;" - "syscall;" - : - : [killnr] "i"(__NR_tgkill), [parent] "rm"(parent), - [tid] "rm"(parent_tid), [sig] "i"(SIGUSR1) - : "rax", "rdi", "rsi", "rdx", - // Clobbered by syscall. - "rcx", "r11"); + asm volatile("syscall;" + : "=a"(ret) + : "a"(__NR_tgkill), "D"(parent), "S"(parent_tid), "d"(SIGUSR1) + : // Clobbered by syscall. + "rcx", "r11"); #elif __aarch64__ - asm volatile( - "mov x8, %0\n" - "mov x0, %1\n" - "mov x1, %2\n" - "mov x2, %3\n" - "svc #0\n" ::"N"(__NR_tgkill), - "r"((uint64_t)parent), "r"((uint64_t)parent_tid), "N"(SIGUSR1)); + register uint64_t x8 __asm__("x8") = __NR_tgkill; + register uint64_t x0 __asm__("x0") = parent; + register uint64_t x1 __asm__("x1") = parent_tid; + register uint64_t x2 __asm__("x2") = SIGUSR1; + asm volatile("svc #0\n" : "=r"(x0) : "r"(x0), "r"(x1), "r"(x2), "r"(x8) :); + ret = x0; #endif + EXPECT_EQ(ret, 0); uint64_t got; GET_FP0(got); diff --git a/test/syscalls/linux/fpsig_nested.cc b/test/syscalls/linux/fpsig_nested.cc index 8222cf5ec..0f2368448 100644 --- a/test/syscalls/linux/fpsig_nested.cc +++ b/test/syscalls/linux/fpsig_nested.cc @@ -60,6 +60,7 @@ void sigusr2(int s, siginfo_t* siginfo, void* _uc) { void sigusr1(int s, siginfo_t* siginfo, void* _uc) { uint64_t val = SIGUSR1; + int64_t ret; // Record the value of %xmm0 on entry and then clobber it. GET_FP0(entryxmm[0]); @@ -68,27 +69,20 @@ void sigusr1(int s, siginfo_t* siginfo, void* _uc) { // Send a SIGUSR2 to ourself. The signal mask is configured such that // the SIGUSR2 handler will run before this handler returns. #ifdef __x86_64__ - asm volatile( - "movl %[killnr], %%eax;" - "movl %[pid], %%edi;" - "movl %[tid], %%esi;" - "movl %[sig], %%edx;" - "syscall;" - : - : [killnr] "i"(__NR_tgkill), [pid] "rm"(pid), [tid] "rm"(tid), - [sig] "i"(SIGUSR2) - : "rax", "rdi", "rsi", "rdx", - // Clobbered by syscall. - "rcx", "r11"); + asm volatile("syscall;" + : "=a"(ret) + : "a"(__NR_tgkill), "D"(pid), "S"(tid), "d"(SIGUSR2) + : // Clobbered by syscall. + "rcx", "r11"); #elif __aarch64__ - asm volatile( - "mov x8, %0\n" - "mov x0, %1\n" - "mov x1, %2\n" - "mov x2, %3\n" - "svc #0\n" ::"N"(__NR_tgkill), - "r"((uint64_t)pid), "r"((uint64_t)tid), "N"(SIGUSR2)); + register uint64_t x8 __asm__("x8") = __NR_tgkill; + register uint64_t x0 __asm__("x0") = pid; + register uint64_t x1 __asm__("x1") = tid; + register uint64_t x2 __asm__("x2") = SIGUSR2; + asm volatile("svc #0\n" : "=r"(x0) : "r"(x0), "r"(x1), "r"(x2), "r"(x8) :); + ret = x0; #endif + EXPECT_EQ(ret, 0); // Record value of %xmm0 again to verify that the nested signal handler // does not clobber it. @@ -123,28 +117,22 @@ TEST(FPSigTest, NestedSignals) { uint64_t expected = 0xdeadbeeffacefeed; SET_FP0(expected); + int64_t ret; #ifdef __x86_64__ - asm volatile( - "movl %[killnr], %%eax;" - "movl %[pid], %%edi;" - "movl %[tid], %%esi;" - "movl %[sig], %%edx;" - "syscall;" - : - : [killnr] "i"(__NR_tgkill), [pid] "rm"(pid), [tid] "rm"(tid), - [sig] "i"(SIGUSR1) - : "rax", "rdi", "rsi", "rdx", - // Clobbered by syscall. - "rcx", "r11"); + asm volatile("syscall;" + : "=a"(ret) + : "a"(__NR_tgkill), "D"(pid), "S"(tid), "d"(SIGUSR1) + : // Clobbered by syscall. + "rcx", "r11"); #elif __aarch64__ - asm volatile( - "mov x8, %0\n" - "mov x0, %1\n" - "mov x1, %2\n" - "mov x2, %3\n" - "svc #0\n" ::"N"(__NR_tgkill), - "r"((uint64_t)pid), "r"((uint64_t)tid), "N"(SIGUSR1)); + register uint64_t x8 __asm__("x8") = __NR_tgkill; + register uint64_t x0 __asm__("x0") = pid; + register uint64_t x1 __asm__("x1") = tid; + register uint64_t x2 __asm__("x2") = SIGUSR1; + asm volatile("svc #0\n" : "=r"(x0) : "r"(x0), "r"(x1), "r"(x2), "r"(x8) :); + ret = x0; #endif + EXPECT_EQ(ret, 0); uint64_t got; GET_FP0(got); @@ -155,8 +143,10 @@ TEST(FPSigTest, NestedSignals) { // - sigreturn(2) must restore fpstate of the interrupted context. // EXPECT_EQ(expected, got); +#ifdef __x86_64__ EXPECT_EQ(entryxmm[0], 0); EXPECT_EQ(entryxmm[1], 0); +#endif EXPECT_EQ(exitxmm[0], SIGUSR1); EXPECT_EQ(exitxmm[1], SIGUSR2); } diff --git a/test/syscalls/linux/sigreturn_arm64.cc b/test/syscalls/linux/sigreturn_arm64.cc index 2c19e2984..897b5bf95 100644 --- a/test/syscalls/linux/sigreturn_arm64.cc +++ b/test/syscalls/linux/sigreturn_arm64.cc @@ -84,8 +84,9 @@ TEST(SigreturnTest, CheckX7) { uint64_t x7 = kOrigX7; - testX7(&x7, __NR_tgkill, getpid(), syscall(__NR_gettid), SIGVTALRM); + int ret = testX7(&x7, __NR_tgkill, getpid(), syscall(__NR_gettid), SIGVTALRM); + EXPECT_EQ(ret, 0); // The following check verifies that %x7 was not clobbered // when returning from the signal handler (via sigreturn(2)). EXPECT_EQ(x7, ~kOrigX7);