From 791a3d1b078a2d361996f84ff08f0ed557f1f8ec Mon Sep 17 00:00:00 2001 From: "R. Christian McDonald" Date: Sat, 20 May 2023 09:02:38 -0400 Subject: [PATCH] sysutils/flashrom: sync upstream to fix local build --- sysutils/flashrom/Makefile | 4 +- sysutils/flashrom/distinfo | 6 +- sysutils/flashrom/files/patch-denverton | 133 ------------------------ 3 files changed, 5 insertions(+), 138 deletions(-) delete mode 100644 sysutils/flashrom/files/patch-denverton diff --git a/sysutils/flashrom/Makefile b/sysutils/flashrom/Makefile index 77e83c20c334..1c0177093126 100644 --- a/sysutils/flashrom/Makefile +++ b/sysutils/flashrom/Makefile @@ -1,11 +1,11 @@ PORTNAME= flashrom -PORTVERSION= 1.2.1 +PORTVERSION= 1.3.0 DISTVERSIONPREFIX= v PORTREVISION= 1 CATEGORIES= sysutils MASTER_SITES= https://download.flashrom.org/releases/ -MAINTAINER= mizhka@gmail.com +MAINTAINER= mizhka@FreeBSD.org COMMENT= Utility for reading, writing, verifying, and erasing flash ROM chips WWW= https://www.flashrom.org/ diff --git a/sysutils/flashrom/distinfo b/sysutils/flashrom/distinfo index ddfdd99d06bc..63e7388bd809 100644 --- a/sysutils/flashrom/distinfo +++ b/sysutils/flashrom/distinfo @@ -1,3 +1,3 @@ -TIMESTAMP = 1673337682 -SHA256 (flashrom-v1.2.1.tar.bz2) = 89a7ff5beb08c89b8795bbd253a51b9453547a864c31793302296b56bbc56d65 -SIZE (flashrom-v1.2.1.tar.bz2) = 365512 +TIMESTAMP = 1677403671 +SHA256 (flashrom-v1.3.0.tar.bz2) = a053234453ccd012e79f3443bdcc61625cf97b7fd7cb4cdd8bfbffbe8b149623 +SIZE (flashrom-v1.3.0.tar.bz2) = 489782 diff --git a/sysutils/flashrom/files/patch-denverton b/sysutils/flashrom/files/patch-denverton deleted file mode 100644 index a1014244137f..000000000000 --- a/sysutils/flashrom/files/patch-denverton +++ /dev/null @@ -1,133 +0,0 @@ ---- chipset_enable.c.orig 2020-02-09 06:00:51 UTC -+++ chipset_enable.c -@@ -31,6 +31,7 @@ - #include - #include - #include -+#include - #include "flash.h" - #include "programmer.h" - #include "hwaccess.h" -@@ -896,7 +897,11 @@ static int enable_flash_pch100_or_c620( - msg_perr("Can't allocate PCI accessor.\n"); - return ret; - } -+#ifdef __FreeBSD__ -+ pci_acc->method = PCI_ACCESS_FBSD_DEVICE; -+#else - pci_acc->method = PCI_ACCESS_I386_TYPE1; -+#endif - pci_init(pci_acc); - register_shutdown(enable_flash_pch100_shutdown, pci_acc); - -@@ -2015,6 +2020,7 @@ const struct penable chipset_enables[] = { - {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100}, - {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100}, - {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100}, -+ {0x8086, 0x19e0, B_S, NT, "Intel", "Denverton SoC", enable_flash_c620}, - {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, - {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, - {0x8086, 0xa1c3, B_S, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620}, ---- flashchips.h.orig 2020-01-20 13:02:48 UTC -+++ flashchips.h -@@ -938,6 +938,7 @@ - #define WINBOND_NEX_W25Q32_W 0x6016 /* W25Q32DW; W25Q32FV in QPI mode */ - #define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */ - #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ -+#define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256FW; Not supported W25Q256FV in QPI mode */ - #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ - #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ - #define WINBOND_NEX_W25Q128_DTR 0x8018 /* W25Q128JW_DTR */ ---- flashrom.c.orig 2019-12-31 17:25:41 UTC -+++ flashrom.c -@@ -1051,7 +1051,22 @@ void unmap_flash(struct flashctx *flash) - } - - if (flash->virtual_memory != (chipaddr)ERROR_PTR) { -- programmer_unmap_flash_region((void *)flash->virtual_memory, flash->chip->total_size * 1024); -+ -+ chipsize_t size = flash->chip->total_size; -+ -+ if (flash->chip->bustype == BUS_PROG) { -+ // INTEL platform C3000 has HW specific devices (APIC) mapped in the upper 32 Meg at address 0xFEE0_0000 to FEEF_FFFF -+ // Since HW sequencing does not need mapping for 32 Meg part restrict it to 16 Meg to operate HW sequencing path(i.e. only unmap 16 Meg) -+ if (flash->chip->total_size > 0x4000) -+ size = 0x4000; -+ msg_pdbg2("%s - using HW seq - unmap flash chip %s with total size %x change to %x\n",__func__, flash->chip->name, flash->chip->total_size, size); -+ } -+ -+ size = size * 1024; -+ -+ msg_pdbg2("%s - unmap flash chip %s at total size %x\n",__func__, flash->chip->name, size); -+ -+ programmer_unmap_flash_region((void *)flash->virtual_memory, size); - flash->physical_memory = 0; - flash->virtual_memory = (chipaddr)ERROR_PTR; - } -@@ -1069,8 +1084,21 @@ int map_flash(struct flashctx *flash) - if (flash->chip->total_size == 0) - return 0; - -- const chipsize_t size = flash->chip->total_size * 1024; -+ chipsize_t size = flash->chip->total_size; -+ -+ if (flash->chip->bustype == BUS_PROG) { -+ // INTEL platform C3000 has HW specific devices (APIC) mapped in the upper 32 Meg at address 0xFEE0_0000 to FEEF_FFFF -+ // Since HW sequencing does not need mapping for 32 Meg part restrict it to 16 Meg to operate HW sequencing path. -+ if (flash->chip->total_size > 0x4000) -+ size = 0x4000; -+ msg_pdbg2("%s - using HW seq - map flash chip %s with total size %x change to %x\n",__func__, flash->chip->name, flash->chip->total_size, size); -+ } -+ -+ size = size * 1024; - uintptr_t base = flashbase ? flashbase : (0xffffffff - size + 1); -+ -+ msg_pdbg2("%s - map flash chip %s at total size %x\n",__func__, flash->chip->name, size); -+ - void *addr = programmer_map_flash_region(flash->chip->name, base, size); - if (addr == ERROR_PTR) { - msg_perr("Could not map flash chip %s at 0x%0*" PRIxPTR ".\n", ---- ichspi.c.orig 2019-09-24 18:49:09 UTC -+++ ichspi.c -@@ -164,6 +164,7 @@ - #define SSFC_SCF (0x7 << SSFC_SCF_OFF) - #define SSFC_SCF_20MHZ 0x00000000 - #define SSFC_SCF_33MHZ 0x01000000 -+#define SSFC_SCF_48MHZ 0x02000000 - /* 19-23: reserved */ - #define SSFC_RESERVED_MASK 0xf8008100 - -@@ -852,7 +853,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset, - programmer_delay(10); - } - if (!timeout) { -- msg_perr("Error: SCIP never cleared!\n"); -+ msg_perr("%s - Error: SCIP never cleared!\n", __func__); - return 1; - } - -@@ -969,7 +970,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, - programmer_delay(10); - } - if (!timeout) { -- msg_perr("Error: SCIP never cleared!\n"); -+ msg_perr("%s - Error: SCIP never cleared!\n", __func__); - return 1; - } - -@@ -990,8 +991,13 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset, - temp32 |= (SSFS_FDONE | SSFS_FCERR); - REGWRITE32(swseq_data.reg_ssfsc, temp32); - -- /* Use 20 MHz */ -- temp32 |= SSFC_SCF_20MHZ; -+ /* Denverton use 48MHZ for now all others use 20 MHZ */ -+ if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) { -+ temp32 |= SSFC_SCF_48MHZ; -+ } -+ else { -+ temp32 |= SSFC_SCF_20MHZ; -+ } - - /* Set data byte count (DBC) and data cycle bit (DS) */ - if (datalength != 0) {