47 lines
1.6 KiB
C++
47 lines
1.6 KiB
C++
//===-- RISCVInstrInfo.h - RISCV Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVINSTRINFO_H
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#include "RISCVRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "RISCVGenInstrInfo.inc"
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namespace llvm {
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class RISCVInstrInfo : public RISCVGenInstrInfo {
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public:
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RISCVInstrInfo();
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned SrcReg,
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bool IsKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, unsigned DstReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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};
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}
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#endif
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