64ac736ec5
Former-commit-id: f3cc9b82f3e5bd8f0fd3ebc098f789556b44e9cd
24 lines
883 B
TableGen
24 lines
883 B
TableGen
//=- AArch64SVEInstrInfo.td - AArch64 SVE Instructions -*- tablegen -*-----=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Vector Extension (SVE) Instruction definitions.
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//
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//===----------------------------------------------------------------------===//
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let Predicates = [HasSVE] in {
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defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
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defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">;
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defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
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defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
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defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
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defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
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}
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