38 lines
1.5 KiB
TableGen
38 lines
1.5 KiB
TableGen
//=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// ScalarItin contains some old itineraries still used by a
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// handful of instructions. Hopefully, we will be able to get rid of them soon.
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def HexagonV62ItinList : DepScalarItinV62, ScalarItin,
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DepHVXItinV62, HVXItin, PseudoItin {
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list<InstrItinData> ItinList =
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!listconcat(DepScalarItinV62_list, ScalarItin_list,
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DepHVXItinV62_list, HVXItin_list, PseudoItin_list);
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}
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def HexagonItinerariesV62 :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
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CVI_ALL_NOMEM],
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[Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>;
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def HexagonModelV62 : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItinerariesV62;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V62 Resource Definitions -
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//===----------------------------------------------------------------------===//
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