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34 lines
1.4 KiB
LLVM
34 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
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; rdar://10232252
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; Prevent LSR of doing poor choice that cannot be folded in addressing mode
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; Remove the -pre-RA-sched=list-hybrid option after fixing:
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; <rdar://problem/12702735> [ARM64][coalescer] need better register
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; coalescing for simple unit tests.
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; CHECK: testCase
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; CHECK: %while.body{{$}}
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; CHECK: ldr [[STREG:x[0-9]+]], [{{x[0-9]+}}], #8
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; CHECK-NEXT: str [[STREG]], [{{x[0-9]+}}], #8
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; CHECK: %while.end
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define i32 @testCase() nounwind ssp {
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entry:
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br label %while.body
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while.body: ; preds = %while.body, %entry
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%len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
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%pDst.05 = phi i64* [ inttoptr (i64 6442450944 to i64*), %entry ], [ %incdec.ptr1, %while.body ]
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%pSrc.04 = phi i64* [ inttoptr (i64 4294967296 to i64*), %entry ], [ %incdec.ptr, %while.body ]
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%incdec.ptr = getelementptr inbounds i64, i64* %pSrc.04, i64 1
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%tmp = load volatile i64, i64* %pSrc.04, align 8
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%incdec.ptr1 = getelementptr inbounds i64, i64* %pDst.05, i64 1
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store volatile i64 %tmp, i64* %pDst.05, align 8
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%sub = add i64 %len.06, -8
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%cmp = icmp sgt i64 %sub, -1
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br i1 %cmp, label %while.body, label %while.end
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while.end: ; preds = %while.body
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tail call void inttoptr (i64 6442450944 to void ()*)() nounwind
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ret i32 0
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}
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