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585 lines
18 KiB
C++
585 lines
18 KiB
C++
//===- X86Operand.h - Parsed X86 machine instruction ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
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#define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "X86AsmParserCommon.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/SMLoc.h"
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#include <cassert>
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#include <memory>
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namespace llvm {
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand : public MCParsedAsmOperand {
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enum KindTy { Token, Register, Immediate, Memory, Prefix } Kind;
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SMLoc StartLoc, EndLoc;
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SMLoc OffsetOfLoc;
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StringRef SymName;
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void *OpDecl;
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bool AddressOf;
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struct TokOp {
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const char *Data;
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unsigned Length;
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};
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struct RegOp {
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unsigned RegNo;
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};
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struct PrefOp {
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unsigned Prefixes;
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};
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struct ImmOp {
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const MCExpr *Val;
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};
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struct MemOp {
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unsigned SegReg;
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const MCExpr *Disp;
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unsigned BaseReg;
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unsigned IndexReg;
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unsigned Scale;
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unsigned Size;
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unsigned ModeSize;
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/// If the memory operand is unsized and there are multiple instruction
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/// matches, prefer the one with this size.
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unsigned FrontendSize;
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};
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union {
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struct TokOp Tok;
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struct RegOp Reg;
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struct ImmOp Imm;
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struct MemOp Mem;
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struct PrefOp Pref;
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};
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X86Operand(KindTy K, SMLoc Start, SMLoc End)
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: Kind(K), StartLoc(Start), EndLoc(End) {}
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StringRef getSymName() override { return SymName; }
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void *getOpDecl() override { return OpDecl; }
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const override { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const override { return EndLoc; }
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/// getLocRange - Get the range between the first and last token of this
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/// operand.
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SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
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/// getOffsetOfLoc - Get the location of the offset operator.
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SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
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void print(raw_ostream &OS) const override {}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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void setTokenValue(StringRef Value) {
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assert(Kind == Token && "Invalid access!");
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Tok.Data = Value.data();
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Tok.Length = Value.size();
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}
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unsigned getReg() const override {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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unsigned getPrefix() const {
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assert(Kind == Prefix && "Invalid access!");
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return Pref.Prefixes;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getMemDisp() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Disp;
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}
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unsigned getMemSegReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.SegReg;
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}
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unsigned getMemBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.BaseReg;
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}
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unsigned getMemIndexReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg;
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}
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unsigned getMemScale() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Scale;
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}
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unsigned getMemModeSize() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.ModeSize;
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}
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unsigned getMemFrontendSize() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.FrontendSize;
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}
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bool isToken() const override {return Kind == Token; }
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bool isImm() const override { return Kind == Immediate; }
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bool isImmSExti16i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti16i8Value(CE->getValue());
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}
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bool isImmSExti32i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti32i8Value(CE->getValue());
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}
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bool isImmSExti64i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti64i8Value(CE->getValue());
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}
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bool isImmSExti64i32() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti64i32Value(CE->getValue());
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}
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bool isImmUnsignedi8() const {
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if (!isImm()) return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return true;
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return isImmUnsignedi8Value(CE->getValue());
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}
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bool isOffsetOf() const override {
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return OffsetOfLoc.getPointer();
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}
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bool needAddressOf() const override {
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return AddressOf;
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}
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bool isMem() const override { return Kind == Memory; }
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bool isMemUnsized() const {
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return Kind == Memory && Mem.Size == 0;
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}
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bool isMem8() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 8);
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}
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bool isMem16() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 16);
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}
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bool isMem32() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 32);
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}
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bool isMem64() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 64);
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}
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bool isMem80() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 80);
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}
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bool isMem128() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 128);
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}
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bool isMem256() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 256);
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}
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bool isMem512() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 512);
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}
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bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
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}
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bool isMem64_RC128() const {
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return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
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}
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bool isMem128_RC128() const {
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return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
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}
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bool isMem128_RC256() const {
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return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM15);
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}
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bool isMem256_RC128() const {
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return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15);
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}
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bool isMem256_RC256() const {
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return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
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}
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bool isMem64_RC128X() const {
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return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31);
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}
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bool isMem128_RC128X() const {
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return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31);
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}
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bool isMem128_RC256X() const {
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return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM31);
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}
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bool isMem256_RC128X() const {
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return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31);
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}
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bool isMem256_RC256X() const {
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return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM31);
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}
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bool isMem256_RC512() const {
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return isMem256() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
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}
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bool isMem512_RC256X() const {
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return isMem512() && isMemIndexReg(X86::YMM0, X86::YMM31);
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}
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bool isMem512_RC512() const {
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return isMem512() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
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}
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bool isAbsMem() const {
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return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
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!getMemIndexReg() && getMemScale() == 1;
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}
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bool isAVX512RC() const{
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return isImm();
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}
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bool isAbsMem16() const {
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return isAbsMem() && Mem.ModeSize == 16;
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}
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bool isSrcIdx() const {
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return !getMemIndexReg() && getMemScale() == 1 &&
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(getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
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getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
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cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
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}
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bool isSrcIdx8() const {
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return isMem8() && isSrcIdx();
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}
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bool isSrcIdx16() const {
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return isMem16() && isSrcIdx();
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}
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bool isSrcIdx32() const {
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return isMem32() && isSrcIdx();
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}
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bool isSrcIdx64() const {
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return isMem64() && isSrcIdx();
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}
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bool isDstIdx() const {
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return !getMemIndexReg() && getMemScale() == 1 &&
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(getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
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(getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
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getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
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cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
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}
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bool isDstIdx8() const {
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return isMem8() && isDstIdx();
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}
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bool isDstIdx16() const {
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return isMem16() && isDstIdx();
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}
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bool isDstIdx32() const {
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return isMem32() && isDstIdx();
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}
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bool isDstIdx64() const {
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return isMem64() && isDstIdx();
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}
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bool isMemOffs() const {
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return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
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getMemScale() == 1;
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}
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bool isMemOffs16_8() const {
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return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
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}
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bool isMemOffs16_16() const {
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return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
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}
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bool isMemOffs16_32() const {
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return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
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}
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bool isMemOffs32_8() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
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}
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bool isMemOffs32_16() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
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}
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bool isMemOffs32_32() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
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}
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bool isMemOffs32_64() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
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}
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bool isMemOffs64_8() const {
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return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
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}
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bool isMemOffs64_16() const {
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return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
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}
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bool isMemOffs64_32() const {
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return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
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}
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bool isMemOffs64_64() const {
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return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
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}
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bool isPrefix() const { return Kind == Prefix; }
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bool isReg() const override { return Kind == Register; }
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bool isGR32orGR64() const {
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return Kind == Register &&
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(X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
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X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible.
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::createImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::createExpr(Expr));
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getReg()));
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}
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static unsigned getGR32FromGR64(unsigned RegNo) {
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switch (RegNo) {
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default: llvm_unreachable("Unexpected register");
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case X86::RAX: return X86::EAX;
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case X86::RCX: return X86::ECX;
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case X86::RDX: return X86::EDX;
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case X86::RBX: return X86::EBX;
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case X86::RBP: return X86::EBP;
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case X86::RSP: return X86::ESP;
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case X86::RSI: return X86::ESI;
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case X86::RDI: return X86::EDI;
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case X86::R8: return X86::R8D;
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case X86::R9: return X86::R9D;
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case X86::R10: return X86::R10D;
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case X86::R11: return X86::R11D;
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case X86::R12: return X86::R12D;
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case X86::R13: return X86::R13D;
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case X86::R14: return X86::R14D;
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case X86::R15: return X86::R15D;
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case X86::RIP: return X86::EIP;
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}
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}
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void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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unsigned RegNo = getReg();
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if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
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RegNo = getGR32FromGR64(RegNo);
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Inst.addOperand(MCOperand::createReg(RegNo));
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}
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void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 5) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::createImm(getMemScale()));
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Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
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addExpr(Inst, getMemDisp());
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Inst.addOperand(MCOperand::createReg(getMemSegReg()));
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}
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void addAbsMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 1) && "Invalid number of operands!");
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// Add as immediates when possible.
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
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Inst.addOperand(MCOperand::createImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::createExpr(getMemDisp()));
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}
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void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
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assert((N == 2) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::createReg(getMemSegReg()));
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}
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void addDstIdxOperands(MCInst &Inst, unsigned N) const {
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assert((N == 1) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
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}
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void addMemOffsOperands(MCInst &Inst, unsigned N) const {
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assert((N == 2) && "Invalid number of operands!");
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// Add as immediates when possible.
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
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Inst.addOperand(MCOperand::createImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::createExpr(getMemDisp()));
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Inst.addOperand(MCOperand::createReg(getMemSegReg()));
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}
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static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
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SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
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auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
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Res->Tok.Data = Str.data();
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Res->Tok.Length = Str.size();
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return Res;
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}
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static std::unique_ptr<X86Operand>
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CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
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bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
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StringRef SymName = StringRef(), void *OpDecl = nullptr) {
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auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
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Res->Reg.RegNo = RegNo;
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Res->AddressOf = AddressOf;
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Res->OffsetOfLoc = OffsetOfLoc;
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|
Res->SymName = SymName;
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Res->OpDecl = OpDecl;
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return Res;
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|
}
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|
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static std::unique_ptr<X86Operand>
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|
CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) {
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|
auto Res = llvm::make_unique<X86Operand>(Prefix, StartLoc, EndLoc);
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|
Res->Pref.Prefixes = Prefixes;
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|
return Res;
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|
}
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|
|
|
static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
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|
SMLoc StartLoc, SMLoc EndLoc) {
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|
auto Res = llvm::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
|
|
Res->Imm.Val = Val;
|
|
return Res;
|
|
}
|
|
|
|
/// Create an absolute memory operand.
|
|
static std::unique_ptr<X86Operand>
|
|
CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
|
|
unsigned Size = 0, StringRef SymName = StringRef(),
|
|
void *OpDecl = nullptr, unsigned FrontendSize = 0) {
|
|
auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
|
|
Res->Mem.SegReg = 0;
|
|
Res->Mem.Disp = Disp;
|
|
Res->Mem.BaseReg = 0;
|
|
Res->Mem.IndexReg = 0;
|
|
Res->Mem.Scale = 1;
|
|
Res->Mem.Size = Size;
|
|
Res->Mem.ModeSize = ModeSize;
|
|
Res->Mem.FrontendSize = FrontendSize;
|
|
Res->SymName = SymName;
|
|
Res->OpDecl = OpDecl;
|
|
Res->AddressOf = false;
|
|
return Res;
|
|
}
|
|
|
|
/// Create a generalized memory operand.
|
|
static std::unique_ptr<X86Operand>
|
|
CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
|
|
unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
|
|
SMLoc EndLoc, unsigned Size = 0, StringRef SymName = StringRef(),
|
|
void *OpDecl = nullptr, unsigned FrontendSize = 0) {
|
|
// We should never just have a displacement, that should be parsed as an
|
|
// absolute memory operand.
|
|
assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
|
|
|
|
// The scale should always be one of {1,2,4,8}.
|
|
assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
|
|
"Invalid scale!");
|
|
auto Res = llvm::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
|
|
Res->Mem.SegReg = SegReg;
|
|
Res->Mem.Disp = Disp;
|
|
Res->Mem.BaseReg = BaseReg;
|
|
Res->Mem.IndexReg = IndexReg;
|
|
Res->Mem.Scale = Scale;
|
|
Res->Mem.Size = Size;
|
|
Res->Mem.ModeSize = ModeSize;
|
|
Res->Mem.FrontendSize = FrontendSize;
|
|
Res->SymName = SymName;
|
|
Res->OpDecl = OpDecl;
|
|
Res->AddressOf = false;
|
|
return Res;
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
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