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250 lines
9.2 KiB
TableGen
250 lines
9.2 KiB
TableGen
//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Addressing modes for load/store instructions
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class AddrModeType<bits<3> value> {
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bits<3> Value = value;
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}
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def NoAddrMode : AddrModeType<0>; // No addressing mode
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def Absolute : AddrModeType<1>; // Absolute addressing mode
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def AbsoluteSet : AddrModeType<2>; // Absolute set addressing mode
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def BaseImmOffset : AddrModeType<3>; // Indirect with offset
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def BaseLongOffset : AddrModeType<4>; // Indirect with long offset
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def BaseRegOffset : AddrModeType<5>; // Indirect with register offset
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def PostInc : AddrModeType<6>; // Post increment addressing mode
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class MemAccessSize<bits<4> value> {
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bits<4> Value = value;
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}
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// These numbers must match the MemAccessSize enumeration values in
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// HexagonBaseInfo.h.
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def NoMemAccess : MemAccessSize<0>;
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def ByteAccess : MemAccessSize<1>;
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def HalfWordAccess : MemAccessSize<2>;
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def WordAccess : MemAccessSize<3>;
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def DoubleWordAccess : MemAccessSize<4>;
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def HVXVectorAccess : MemAccessSize<5>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Declaration +
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//===----------------------------------------------------------------------===//
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class OpcodeHexagon {
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field bits<32> Inst = ?; // Default to an invalid insn.
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bits<4> IClass = 0; // ICLASS
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bits<1> zero = 0;
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let Inst{31-28} = IClass;
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}
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class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr, InstrItinClass itin, IType type>
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: Instruction {
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let Namespace = "Hexagon";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Constraints = cstr;
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let Itinerary = itin;
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let Size = 4;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
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// mainly used for ARM, but Tablegen expects this field to exist or it fails
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// to build the decode table.
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field bits<32> SoftFail = 0;
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// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
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// Instruction type according to the ISA.
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IType Type = type;
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let TSFlags{5-0} = Type.Value;
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// Solo instructions, i.e., those that cannot be in a packet with others.
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bits<1> isSolo = 0;
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let TSFlags{6} = isSolo;
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// Packed only with A or X-type instructions.
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bits<1> isSoloAX = 0;
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let TSFlags{7} = isSoloAX;
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// Restricts slot 1 to ALU-only instructions.
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bits<1> isRestrictSlot1AOK = 0;
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let TSFlags{8} = isRestrictSlot1AOK;
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// Predicated instructions.
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bits<1> isPredicated = 0;
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let TSFlags{9} = isPredicated;
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bits<1> isPredicatedFalse = 0;
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let TSFlags{10} = isPredicatedFalse;
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bits<1> isPredicatedNew = 0;
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let TSFlags{11} = isPredicatedNew;
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bits<1> isPredicateLate = 0;
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let TSFlags{12} = isPredicateLate; // Late predicate producer insn.
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// New-value insn helper fields.
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bits<1> isNewValue = 0;
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let TSFlags{13} = isNewValue; // New-value consumer insn.
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bits<1> hasNewValue = 0;
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let TSFlags{14} = hasNewValue; // New-value producer insn.
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bits<3> opNewValue = 0;
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let TSFlags{17-15} = opNewValue; // New-value produced operand.
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bits<1> isNVStorable = 0;
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let TSFlags{18} = isNVStorable; // Store that can become new-value store.
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bits<1> isNVStore = 0;
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let TSFlags{19} = isNVStore; // New-value store insn.
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bits<1> isCVLoadable = 0;
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let TSFlags{20} = isCVLoadable; // Load that can become cur-value load.
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bits<1> isCVLoad = 0;
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let TSFlags{21} = isCVLoad; // Cur-value load insn.
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// Immediate extender helper fields.
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bits<1> isExtendable = 0;
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let TSFlags{22} = isExtendable; // Insn may be extended.
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bits<1> isExtended = 0;
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let TSFlags{23} = isExtended; // Insn must be extended.
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bits<3> opExtendable = 0;
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let TSFlags{26-24} = opExtendable; // Which operand may be extended.
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bits<1> isExtentSigned = 0;
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let TSFlags{27} = isExtentSigned; // Signed or unsigned range.
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bits<5> opExtentBits = 0;
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let TSFlags{32-28} = opExtentBits; //Number of bits of range before extending.
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bits<2> opExtentAlign = 0;
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let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending.
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bit cofMax1 = 0;
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let TSFlags{35} = cofMax1;
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bit cofRelax1 = 0;
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let TSFlags{36} = cofRelax1;
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bit cofRelax2 = 0;
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let TSFlags{37} = cofRelax2;
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bit isRestrictNoSlot1Store = 0;
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let TSFlags{38} = isRestrictNoSlot1Store;
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// Addressing mode for load/store instructions.
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AddrModeType addrMode = NoAddrMode;
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let TSFlags{43-41} = addrMode.Value;
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// Memory access size for mem access instructions (load/store)
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MemAccessSize accessSize = NoMemAccess;
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let TSFlags{47-44} = accessSize.Value;
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bits<1> isTaken = 0;
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let TSFlags {48} = isTaken; // Branch prediction.
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bits<1> isFP = 0;
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let TSFlags {49} = isFP; // Floating-point.
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bits<1> isSomeOK = 0;
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let TSFlags {50} = isSomeOK; // Relax some grouping constraints.
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bits<1> hasNewValue2 = 0;
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let TSFlags{51} = hasNewValue2; // Second New-value producer insn.
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bits<3> opNewValue2 = 0;
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let TSFlags{54-52} = opNewValue2; // Second New-value produced operand.
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bits<1> isAccumulator = 0;
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let TSFlags{55} = isAccumulator;
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bits<1> prefersSlot3 = 0;
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let TSFlags{56} = prefersSlot3; // Complex XU
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bits<1> hasTmpDst = 0;
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let TSFlags{59} = hasTmpDst; // v65 : 'fake" register VTMP is set
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bit CVINew = 0;
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let TSFlags{61} = CVINew;
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// Fields used for relation models.
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bit isNonTemporal = 0;
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string isNT = ""; // set to "true" for non-temporal vector stores.
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string BaseOpcode = "";
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string CextOpcode = "";
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string PredSense = "";
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string PNewValue = "";
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string NValueST = ""; // Set to "true" for new-value stores.
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string InputType = ""; // Input is "imm" or "reg" type.
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string isFloat = "false"; // Set to "true" for the floating-point load/store.
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string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
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let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
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"");
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let PNewValue = !if(isPredicatedNew, "new", "");
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let NValueST = !if(isNVStore, "true", "false");
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let isNT = !if(isNonTemporal, "true", "false");
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let hasSideEffects = 0;
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// *** Must match MCTargetDesc/HexagonBaseInfo.h ***
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}
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class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> :
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InstHexagon<outs, ins, asmstr, [], "", itin, type>;
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//===----------------------------------------------------------------------===//
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// Instruction Classes Definitions +
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//===----------------------------------------------------------------------===//
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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let mayLoad = 1 in
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class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
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class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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let mayStore = 1 in
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class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = tc_ENDLOOP>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
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OpcodeHexagon;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDO, TypePSEUDO>,
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OpcodeHexagon;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr="">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, PSEUDOM, TypePSEUDO>,
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OpcodeHexagon;
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//===----------------------------------------------------------------------===//
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// Instruction Classes Definitions -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// V4 Instruction Format Definitions +
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//===----------------------------------------------------------------------===//
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include "HexagonInstrFormatsV4.td"
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//===----------------------------------------------------------------------===//
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// V60+ Instruction Format Definitions +
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//===----------------------------------------------------------------------===//
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include "HexagonInstrFormatsV60.td"
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include "HexagonInstrFormatsV65.td"
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