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LLVM 6.0.0 Release Notes
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========================
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.. contents::
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:local:
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release 6.0.0. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <http://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
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have questions or comments, the `LLVM Developer's Mailing List
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<http://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
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them.
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Non-comprehensive list of changes in this release
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=================================================
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* Support for `retpolines <https://support.google.com/faqs/answer/7625886>`_
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was added to help mitigate "branch target injection" (variant #2) of the
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"Spectre" speculative side channels described by `Project Zero
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<https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html>`_
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and the `Spectre paper <https://spectreattack.com/spectre.pdf>`_.
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* The ``Redirects`` argument of ``llvm::sys::ExecuteAndWait`` and
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``llvm::sys::ExecuteNoWait`` was changed to an ``ArrayRef`` of optional
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``StringRef``'s to make it safer and more convenient to use.
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* The backend name was added to the Target Registry to allow run-time
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information to be fed back into TableGen. Out-of-tree targets will need to add
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the name used in the `def X : Target` definition to the call to
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`RegisterTarget`.
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* The ``Debugify`` pass was added to ``opt`` to facilitate testing of debug
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info preservation. This pass attaches synthetic ``DILocations`` and
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``DIVariables`` to the instructions in a ``Module``. The ``CheckDebugify``
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pass determines how much of the metadata is lost.
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* Significantly improved quality of CodeView debug info for Windows.
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* Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD
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(ASan, UBsan, TSan, MSan, SafeStack, libFuzzer).
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Changes to the LLVM IR
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----------------------
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* The fast-math-flags (FMF) have been updated. Previously, the 'fast' flag
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indicated that floating-point reassociation was allowed and all other flags
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were set too. The 'fast' flag still exists, but there is a new flag called
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'reassoc' to indicate specifically that reassociation is allowed. A new bit
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called 'afn' was also added to selectively allow approximations for common
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mathlib functions like square-root. The new flags provide more flexibility
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to enable/disable specific floating-point optimizations. Making the
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optimizer respond appropriately to these flags is an ongoing effort.
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Changes to the AArch64 Target
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-----------------------------
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* Enabled the new GlobalISel instruction selection framework by default at ``-O0``.
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Changes to the ARM Target
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-------------------------
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* Support for enabling SjLj exception handling on platforms where it
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isn't the default.
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Changes to the Hexagon Target
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-----------------------------
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* The Hexagon backend now supports V65 ISA.
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* The ``-mhvx`` option now takes an optional value that specifies the ISA
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version of the HVX coprocessor. The available values are v60, v62 and v65.
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By default, the value is set to be the same as the CPU version.
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* The compiler option ``-mhvx-double`` is deprecated and will be removed in
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the next release of the compiler. Programmers should use the ``-mhvx-length``
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option to specify the desired vector length: ``-mhvx-length=64b`` for
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64-byte vectors and ``-mhvx-length=128b`` for 128-byte vectors. While the
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current default vector length is 64 bytes, users should always specify the
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length explicitly, since the default value may change in the future.
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* The target feature ``hvx-double`` is deprecated and will be removed in the
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next release. LLVM IR generators should use target features ``hvx-length64b``
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and ``hvx-length128b`` to indicate the vector length. The length should
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always be specified when HVX code generation is enabled.
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Changes to the MIPS Target
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--------------------------
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Fixed numerous bugs:
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* fpowi on MIPS64 giving incorrect results when used with a negative integer.
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* Usage of the asm 'c' constraint with the wrong datatype causing an
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assert/crash.
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* Fixed a conversion bug when using the DSP ASE.
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* Fixed an inconsistency where objects were not marked as using the microMIPS as
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when the micromips function attribute or the ".set micromips" directive was
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used.
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* Reordered the MIPSR6 specific hazard scheduler pass to after the delay slot
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filler, fixing a class of rare edge case bugs where the delay slot filler
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would violate ISA restrictions.
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* Fixed a crash when using a type of unknown size with gp relative addressing.
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* Corrected the j macro for microMIPS.
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* Corrected the encoding of movep for microMIPS32r6.
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* Fixed an issue with the usage of insert instructions having an invalid set of
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operands.
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* Fixed an issue where TLS symbols were not marked as such.
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* Enabled the usage of register scavenging with MSA, due to its shorter offsets
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for loads and stores.
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* Corrected the ELF headers when using the DSP ASE.
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New features:
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* The long branch pass now generates some R6 specific instructions when
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targeting MIPSR6.
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* The delay slot filler now performs more branch conversions if delay slots
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cannot be filled.
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* The MIPS MT ASE is now fully supported.
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* Added support for the ``lapc`` pseudo instruction.
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* Improved the selection of multiple instructions (``dext``, ``nmadd``,
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``nmsub``).
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* Further improved microMIPS codesize reduction.
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Deprecation notices:
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* microMIPS64R6 support was been deprecated since 5.0, and has now been
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completely removed.
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Changes to the SystemZ Target
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-----------------------------
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During this release the SystemZ target has:
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* Added support for 128-bit atomic operations.
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* Added support for the "o" constraint for inline asm statements.
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Changes to the X86 Target
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-------------------------
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During this release the X86 target has:
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* Added support for enabling SjLj exception handling on platforms where it
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isn't the default.
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* Added intrinsics for Intel Extensions: VAES, GFNI, VPCLMULQDQ, AVX512VBMI2, AVX512BITALG, AVX512VNNI.
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* Added support for Intel Icelake CPU.
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* Fixed some X87 codegen bugs.
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* Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge, Haswell, Broadwell, and Skylake CPUs.
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* Improved scheduler model for AMD Jaguar CPUs.
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* Improved llvm-mc's disassembler for some EVEX encoded instructions.
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* Add support for i8 and i16 vector signed/unsigned min/max horizontal reductions.
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* Improved codegen for memory comparisons
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* Improved codegen for i32 vector multiplies
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* Improved codegen for scalar integer absolute values
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* Improved codegen for vector integer rotations (XOP and AVX512)
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* Improved codegen of data being transferred between GPRs and K-registers.
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* Improved codegen for vector truncations.
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* Improved folding of address computations into gather/scatter instructions.
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* Gained initial support recognizing variable shuffles from vector element extracts and inserts.
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* Improved documentation for SSE/AVX intrinsics in intrin.h header files.
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* Gained support for emitting `retpolines
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<https://support.google.com/faqs/answer/7625886>`_, including automatic
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insertion of the necessary thunks or using external thunks.
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External Open Source Projects Using LLVM 6
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==========================================
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LDC - the LLVM-based D compiler
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-------------------------------
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`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
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pragmatically combines efficiency, control, and modeling power, with safety and
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programmer productivity. D supports powerful concepts like Compile-Time Function
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Execution (CTFE) and Template Meta-Programming, provides an innovative approach
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to concurrency and offers many classical paradigms.
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`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
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combined with LLVM as backend to produce efficient native code. LDC targets
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x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux on ARM
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and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64
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are underway.
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JFS - JIT Fuzzing Solver
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------------------------
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`JFS <https://github.com/delcypher/jfs>`_ is an experimental constraint solver
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designed to investigate using coverage guided fuzzing as an incomplete strategy
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for solving boolean, BitVector, and floating-point constraints.
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It is built on top of LLVM, Clang, LibFuzzer, and Z3.
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The solver works by generating a C++ program where the reachability of an
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`abort()` statement is equivalent to finding a satisfying assignment to the
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constraints. This program is then compiled by Clang with `SanitizerCoverage
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<https://releases.llvm.org/6.0.0/tools/clang/docs/SanitizerCoverage.html>`_
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instrumentation and then fuzzed using :doc:`LibFuzzer <LibFuzzer>`.
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Zig Programming Language
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------------------------
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`Zig <http://ziglang.org>`_ is an open-source programming language designed
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for robustness, optimality, and clarity. It is intended to replace C. It
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provides high level features such as Generics,
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Compile Time Function Execution, and Partial Evaluation, yet exposes low level
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LLVM IR features such as Aliases. Zig uses Clang to provide automatic
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import of .h symbols - even inline functions and macros. Zig uses LLD combined
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with lazily building compiler-rt to provide out-of-the-box cross-compiling for
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all supported targets.
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<http://llvm.org/>`_, in particular in the `documentation
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<http://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Subversion version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `mailing lists <http://llvm.org/docs/#maillist>`_.
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