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100 lines
3.4 KiB
LLVM
100 lines
3.4 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i64 0, align 8
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_iltsll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori r3, [[REG4]], 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll_sext:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-NEXT: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK-NEXT: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK-NEXT: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NEXT: neg r3, [[REG5]]
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @test_iltsll_sext_z(i64 %a) {
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; CHECK-LABEL: test_iltsll_sext_z:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 0
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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; Function Attrs: norecurse nounwind
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define void @test_iltsll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK-NOT: neg {{r[0-9]+}}, [[REG5]]
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entry:
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%cmp = icmp slt i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_iltsll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_iltsll_sext_store:
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; CHECK: # %bb.0: # %entry
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; CHECK: sradi [[REG1:r[0-9]+]], r3, 63
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; CHECK: rldicl [[REG2:r[0-9]+]], r4, 1, 63
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; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
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; CHECK: adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
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; CHECK: xori [[REG5:r[0-9]+]], [[REG4]], 1
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; CHECK: neg {{r[0-9]+}}, [[REG5]]
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entry:
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%cmp = icmp slt i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @test_iltsll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_iltsll_sext_z_store:
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; CHECK: sradi r3, r3, 63
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entry:
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%cmp = icmp slt i64 %a, 0
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%conv2 = sext i1 %cmp to i64
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store i64 %conv2, i64* @glob, align 8
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ret void
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}
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