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72 lines
2.2 KiB
LLVM
72 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx -mcpu=pwr8 < %s | \
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; RUN: FileCheck %s --implicit-check-not lxvd2x --implicit-check-not lfs
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=-altivec -mcpu=pwr8 -mattr=-vsx < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-NVSXALT --implicit-check-not xxlxor \
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; RUN: --implicit-check-not vxor
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define signext i32 @t1(float %x) local_unnamed_addr #0 {
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entry:
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%cmp = fcmp ogt float %x, 0.000000e+00
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%tmp = select i1 %cmp, i32 43, i32 11
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ret i32 %tmp
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; CHECK-LABEL: t1:
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; CHECK: xxlxor [[REG1:[0-9]+]], [[REG1]], [[REG1]]
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; CHECK: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG1]]
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; CHECK: blr
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; CHECK-NVSXALT: lfs [[REG1:[0-9]+]]
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; CHECK-NVSXALT: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG1]]
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; CHECK-NVSXALT: blr
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}
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define signext i32 @t2(double %x) local_unnamed_addr #0 {
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entry:
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%cmp = fcmp ogt double %x, 0.000000e+00
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%tmp = select i1 %cmp, i32 43, i32 11
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ret i32 %tmp
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; CHECK-LABEL: t2:
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; CHECK: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
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; CHECK: xscmpudp {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
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; CHECK: blr
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; CHECK-NVSXALT: lfs [[REG2:[0-9]+]]
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; CHECK-NVSXALT: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
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; CHECK-NVSXALT: blr
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}
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define signext i32 @t3(ppc_fp128 %x) local_unnamed_addr #0 {
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entry:
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%cmp = fcmp ogt ppc_fp128 %x, 0xM00000000000000000000000000000000
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%tmp = select i1 %cmp, i32 43, i32 11
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ret i32 %tmp
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; CHECK-LABEL: t3:
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; CHECK: xxlxor [[REG3:[0-9]+]], [[REG3]], [[REG3]]
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; CHECK: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
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; CHECK: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
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; CHECK: blr
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; CHECK-NVSXALT: lfs [[REG3:[0-9]+]]
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; CHECK-NVSXALT: fcmpu {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
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; CHECK-NVSXALT: blr
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}
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define <2 x double> @t4() local_unnamed_addr #0 {
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ret <2 x double> zeroinitializer
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; CHECK-LABEL: t4:
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; CHECK: xxlxor [[REG4:[0-9]+]], [[REG4]], [[REG4]]
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; CHECK: blr
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; CHECK-NVSXALT: lfs [[REG4:[0-9]+]]
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; CHECK-NVSXALT: fmr {{[0-9]+}}, [[REG4:[0-9]+]]
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; CHECK-NVSXALT: blr
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}
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define <2 x i64> @t5() local_unnamed_addr #0 {
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ret <2 x i64> zeroinitializer
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; CHECK-LABEL: t5:
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; CHECK: xxlxor [[REG5:[0-9]+]], [[REG5]], [[REG5]]
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; CHECK: blr
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; CHECK-NVSXALT: li 3, 0
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; CHECK-NVSXALT-NEXT: li 4, 0
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; CHECK-NVSXALT-NEXT: blr
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}
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