140 lines
5.3 KiB
C++
140 lines
5.3 KiB
C++
//===--- AMDGPUKernelDescriptor.h -------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief AMDGPU kernel descriptor definitions. For more information, visit
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/// https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor-for-gfx6-gfx9
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SUPPORT_AMDGPUKERNELDESCRIPTOR_H
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#define LLVM_SUPPORT_AMDGPUKERNELDESCRIPTOR_H
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#include <cstdint>
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// Creates enumeration entries used for packing bits into integers. Enumeration
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// entries include bit shift amount, bit width, and bit mask.
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#define AMDGPU_BITS_ENUM_ENTRY(name, shift, width) \
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name ## _SHIFT = (shift), \
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name ## _WIDTH = (width), \
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name = (((1 << (width)) - 1) << (shift)) \
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// Gets bits for specified bit mask from specified source.
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#define AMDGPU_BITS_GET(src, mask) \
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((src & mask) >> mask ## _SHIFT) \
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// Sets bits for specified bit mask in specified destination.
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#define AMDGPU_BITS_SET(dst, mask, val) \
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dst &= (~(1 << mask ## _SHIFT) & ~mask); \
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dst |= (((val) << mask ## _SHIFT) & mask) \
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namespace llvm {
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namespace AMDGPU {
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namespace HSAKD {
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/// \brief Floating point rounding modes.
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enum : uint8_t {
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AMDGPU_FLOAT_ROUND_MODE_NEAR_EVEN = 0,
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AMDGPU_FLOAT_ROUND_MODE_PLUS_INFINITY = 1,
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AMDGPU_FLOAT_ROUND_MODE_MINUS_INFINITY = 2,
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AMDGPU_FLOAT_ROUND_MODE_ZERO = 3,
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};
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/// \brief Floating point denorm modes.
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enum : uint8_t {
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AMDGPU_FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0,
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AMDGPU_FLOAT_DENORM_MODE_FLUSH_DST = 1,
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AMDGPU_FLOAT_DENORM_MODE_FLUSH_SRC = 2,
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AMDGPU_FLOAT_DENORM_MODE_FLUSH_NONE = 3,
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};
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/// \brief System VGPR workitem IDs.
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enum : uint8_t {
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AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X = 0,
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AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X_Y = 1,
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AMDGPU_SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2,
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AMDGPU_SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3,
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};
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/// \brief Compute program resource register one layout.
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enum ComputePgmRsrc1 {
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AMDGPU_BITS_ENUM_ENTRY(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6),
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AMDGPU_BITS_ENUM_ENTRY(GRANULATED_WAVEFRONT_SGPR_COUNT, 6, 4),
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AMDGPU_BITS_ENUM_ENTRY(PRIORITY, 10, 2),
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AMDGPU_BITS_ENUM_ENTRY(FLOAT_ROUND_MODE_32, 12, 2),
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AMDGPU_BITS_ENUM_ENTRY(FLOAT_ROUND_MODE_16_64, 14, 2),
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AMDGPU_BITS_ENUM_ENTRY(FLOAT_DENORM_MODE_32, 16, 2),
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AMDGPU_BITS_ENUM_ENTRY(FLOAT_DENORM_MODE_16_64, 18, 2),
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AMDGPU_BITS_ENUM_ENTRY(PRIV, 20, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_DX10_CLAMP, 21, 1),
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AMDGPU_BITS_ENUM_ENTRY(DEBUG_MODE, 22, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_IEEE_MODE, 23, 1),
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AMDGPU_BITS_ENUM_ENTRY(BULKY, 24, 1),
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AMDGPU_BITS_ENUM_ENTRY(CDBG_USER, 25, 1),
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AMDGPU_BITS_ENUM_ENTRY(FP16_OVFL, 26, 1),
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AMDGPU_BITS_ENUM_ENTRY(RESERVED0, 27, 5),
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};
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/// \brief Compute program resource register two layout.
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enum ComputePgmRsrc2 {
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_PRIVATE_SEGMENT_WAVE_OFFSET, 0, 1),
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AMDGPU_BITS_ENUM_ENTRY(USER_SGPR_COUNT, 1, 5),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_TRAP_HANDLER, 6, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_ID_X, 7, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_ID_Y, 8, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_ID_Z, 9, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_SGPR_WORKGROUP_INFO, 10, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_VGPR_WORKITEM_ID, 11, 2),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_ADDRESS_WATCH, 13, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_MEMORY, 14, 1),
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AMDGPU_BITS_ENUM_ENTRY(GRANULATED_LDS_SIZE, 15, 9),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, 24, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_FP_DENORMAL_SOURCE, 25, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, 26, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW, 27, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW, 28, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_IEEE_754_FP_INEXACT, 29, 1),
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AMDGPU_BITS_ENUM_ENTRY(ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO, 30, 1),
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AMDGPU_BITS_ENUM_ENTRY(RESERVED1, 31, 1),
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};
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/// \brief Kernel descriptor layout. This layout should be kept backwards
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/// compatible as it is consumed by the command processor.
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struct KernelDescriptor final {
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uint32_t GroupSegmentFixedSize;
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uint32_t PrivateSegmentFixedSize;
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uint32_t MaxFlatWorkGroupSize;
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uint64_t IsDynamicCallStack : 1;
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uint64_t IsXNACKEnabled : 1;
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uint64_t Reserved0 : 30;
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int64_t KernelCodeEntryByteOffset;
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uint64_t Reserved1[3];
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uint32_t ComputePgmRsrc1;
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uint32_t ComputePgmRsrc2;
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uint64_t EnableSGPRPrivateSegmentBuffer : 1;
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uint64_t EnableSGPRDispatchPtr : 1;
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uint64_t EnableSGPRQueuePtr : 1;
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uint64_t EnableSGPRKernargSegmentPtr : 1;
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uint64_t EnableSGPRDispatchID : 1;
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uint64_t EnableSGPRFlatScratchInit : 1;
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uint64_t EnableSGPRPrivateSegmentSize : 1;
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uint64_t EnableSGPRGridWorkgroupCountX : 1;
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uint64_t EnableSGPRGridWorkgroupCountY : 1;
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uint64_t EnableSGPRGridWorkgroupCountZ : 1;
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uint64_t Reserved2 : 54;
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KernelDescriptor() = default;
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};
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} // end namespace HSAKD
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif // LLVM_SUPPORT_AMDGPUKERNELDESCRIPTOR_H
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