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313 lines
11 KiB
C++
313 lines
11 KiB
C++
//===-- LanaiMCCodeEmitter.cpp - Convert Lanai code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LanaiMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "Lanai.h"
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#include "LanaiAluCode.h"
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#include "MCTargetDesc/LanaiBaseInfo.h"
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#include "MCTargetDesc/LanaiFixupKinds.h"
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#include "MCTargetDesc/LanaiMCExpr.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdint>
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace llvm {
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namespace {
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class LanaiMCCodeEmitter : public MCCodeEmitter {
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public:
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LanaiMCCodeEmitter(const MCInstrInfo &MCII, MCContext &C) {}
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LanaiMCCodeEmitter(const LanaiMCCodeEmitter &) = delete;
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void operator=(const LanaiMCCodeEmitter &) = delete;
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~LanaiMCCodeEmitter() override = default;
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// The functions below are called by TableGen generated functions for getting
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// the binary encoding of instructions/opereands.
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// getBinaryCodeForInstr - TableGen'erated function for getting the
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// binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &Inst,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const;
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// getMachineOpValue - Return binary encoding of operand. If the machine
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// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const;
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unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const;
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unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const;
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unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const;
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unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const;
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void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const override;
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unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
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const MCSubtargetInfo &STI) const;
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unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
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const MCSubtargetInfo &STI) const;
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};
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} // end anonymous namespace
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static Lanai::Fixups FixupKind(const MCExpr *Expr) {
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if (isa<MCSymbolRefExpr>(Expr))
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return Lanai::FIXUP_LANAI_21;
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if (const LanaiMCExpr *McExpr = dyn_cast<LanaiMCExpr>(Expr)) {
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LanaiMCExpr::VariantKind ExprKind = McExpr->getKind();
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switch (ExprKind) {
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case LanaiMCExpr::VK_Lanai_None:
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return Lanai::FIXUP_LANAI_21;
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case LanaiMCExpr::VK_Lanai_ABS_HI:
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return Lanai::FIXUP_LANAI_HI16;
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case LanaiMCExpr::VK_Lanai_ABS_LO:
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return Lanai::FIXUP_LANAI_LO16;
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}
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}
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return Lanai::Fixups(0);
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}
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// getMachineOpValue - Return binary encoding of operand. If the machine
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// operand requires relocation, record the relocation and return zero.
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unsigned LanaiMCCodeEmitter::getMachineOpValue(
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const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const {
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if (MCOp.isReg())
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return getLanaiRegisterNumbering(MCOp.getReg());
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if (MCOp.isImm())
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return static_cast<unsigned>(MCOp.getImm());
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// MCOp must be an expression
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assert(MCOp.isExpr());
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const MCExpr *Expr = MCOp.getExpr();
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// Extract the symbolic reference side of a binary expression.
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if (Expr->getKind() == MCExpr::Binary) {
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const MCBinaryExpr *BinaryExpr = static_cast<const MCBinaryExpr *>(Expr);
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Expr = BinaryExpr->getLHS();
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}
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assert(isa<LanaiMCExpr>(Expr) || Expr->getKind() == MCExpr::SymbolRef);
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// Push fixup (all info is contained within)
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Fixups.push_back(
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MCFixup::create(0, MCOp.getExpr(), MCFixupKind(FixupKind(Expr))));
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return 0;
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}
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// Helper function to adjust P and Q bits on load and store instructions.
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static unsigned adjustPqBits(const MCInst &Inst, unsigned Value,
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unsigned PBitShift, unsigned QBitShift) {
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const MCOperand AluOp = Inst.getOperand(3);
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unsigned AluCode = AluOp.getImm();
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// Set the P bit to one iff the immediate is nonzero and not a post-op
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// instruction.
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const MCOperand Op2 = Inst.getOperand(2);
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Value &= ~(1 << PBitShift);
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if (!LPAC::isPostOp(AluCode) &&
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((Op2.isImm() && Op2.getImm() != 0) ||
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(Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
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Value |= (1 << PBitShift);
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// Set the Q bit to one iff it is a post- or pre-op instruction.
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assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
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"Expected register operand.");
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Value &= ~(1 << QBitShift);
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if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
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(Op2.isReg() && Op2.getReg() != Lanai::R0)))
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Value |= (1 << QBitShift);
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return Value;
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}
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unsigned
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LanaiMCCodeEmitter::adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
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const MCSubtargetInfo &STI) const {
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return adjustPqBits(Inst, Value, 17, 16);
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}
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unsigned
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LanaiMCCodeEmitter::adjustPqBitsSpls(const MCInst &Inst, unsigned Value,
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const MCSubtargetInfo &STI) const {
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return adjustPqBits(Inst, Value, 11, 10);
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}
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void LanaiMCCodeEmitter::encodeInstruction(
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const MCInst &Inst, raw_ostream &Ostream, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const {
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// Get instruction encoding and emit it
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unsigned Value = getBinaryCodeForInstr(Inst, Fixups, SubtargetInfo);
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++MCNumEmitted; // Keep track of the number of emitted insns.
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// Emit bytes in big-endian
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for (int i = (4 - 1) * 8; i >= 0; i -= 8)
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Ostream << static_cast<char>((Value >> i) & 0xff);
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}
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// Encode Lanai Memory Operand
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unsigned LanaiMCCodeEmitter::getRiMemoryOpValue(
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const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const {
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unsigned Encoding;
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const MCOperand Op1 = Inst.getOperand(OpNo + 0);
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const MCOperand Op2 = Inst.getOperand(OpNo + 1);
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const MCOperand AluOp = Inst.getOperand(OpNo + 2);
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assert(Op1.isReg() && "First operand is not register.");
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assert((Op2.isImm() || Op2.isExpr()) &&
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"Second operand is neither an immediate nor an expression.");
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assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
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"Register immediate only supports addition operator");
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Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 18);
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if (Op2.isImm()) {
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assert(isInt<16>(Op2.getImm()) &&
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"Constant value truncated (limited to 16-bit)");
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Encoding |= (Op2.getImm() & 0xffff);
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if (Op2.getImm() != 0) {
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if (LPAC::isPreOp(AluOp.getImm()))
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Encoding |= (0x3 << 16);
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if (LPAC::isPostOp(AluOp.getImm()))
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Encoding |= (0x1 << 16);
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}
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} else
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getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
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return Encoding;
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}
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unsigned LanaiMCCodeEmitter::getRrMemoryOpValue(
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const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const {
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unsigned Encoding;
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const MCOperand Op1 = Inst.getOperand(OpNo + 0);
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const MCOperand Op2 = Inst.getOperand(OpNo + 1);
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const MCOperand AluMCOp = Inst.getOperand(OpNo + 2);
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assert(Op1.isReg() && "First operand is not register.");
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Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 15);
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assert(Op2.isReg() && "Second operand is not register.");
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Encoding |= (getLanaiRegisterNumbering(Op2.getReg()) << 10);
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assert(AluMCOp.isImm() && "Third operator is not immediate.");
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// Set BBB
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unsigned AluOp = AluMCOp.getImm();
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Encoding |= LPAC::encodeLanaiAluCode(AluOp) << 5;
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// Set P and Q
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if (LPAC::isPreOp(AluOp))
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Encoding |= (0x3 << 8);
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if (LPAC::isPostOp(AluOp))
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Encoding |= (0x1 << 8);
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// Set JJJJ
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switch (LPAC::getAluOp(AluOp)) {
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case LPAC::SHL:
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case LPAC::SRL:
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Encoding |= 0x10;
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break;
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case LPAC::SRA:
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Encoding |= 0x18;
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break;
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default:
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break;
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}
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return Encoding;
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}
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unsigned
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LanaiMCCodeEmitter::getSplsOpValue(const MCInst &Inst, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const {
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unsigned Encoding;
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const MCOperand Op1 = Inst.getOperand(OpNo + 0);
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const MCOperand Op2 = Inst.getOperand(OpNo + 1);
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const MCOperand AluOp = Inst.getOperand(OpNo + 2);
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assert(Op1.isReg() && "First operand is not register.");
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assert((Op2.isImm() || Op2.isExpr()) &&
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"Second operand is neither an immediate nor an expression.");
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assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) &&
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"Register immediate only supports addition operator");
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Encoding = (getLanaiRegisterNumbering(Op1.getReg()) << 12);
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if (Op2.isImm()) {
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assert(isInt<10>(Op2.getImm()) &&
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"Constant value truncated (limited to 10-bit)");
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Encoding |= (Op2.getImm() & 0x3ff);
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if (Op2.getImm() != 0) {
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if (LPAC::isPreOp(AluOp.getImm()))
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Encoding |= (0x3 << 10);
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if (LPAC::isPostOp(AluOp.getImm()))
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Encoding |= (0x1 << 10);
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}
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} else
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getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo);
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return Encoding;
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}
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unsigned LanaiMCCodeEmitter::getBranchTargetOpValue(
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const MCInst &Inst, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &SubtargetInfo) const {
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const MCOperand &MCOp = Inst.getOperand(OpNo);
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if (MCOp.isReg() || MCOp.isImm())
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return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
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Fixups.push_back(MCFixup::create(
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0, MCOp.getExpr(), static_cast<MCFixupKind>(Lanai::FIXUP_LANAI_25)));
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return 0;
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}
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#include "LanaiGenMCCodeEmitter.inc"
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} // end namespace llvm
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llvm::MCCodeEmitter *
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llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo,
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const MCRegisterInfo & /*MRI*/,
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MCContext &context) {
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return new LanaiMCCodeEmitter(InstrInfo, context);
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}
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