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464 lines
9.3 KiB
LLVM
464 lines
9.3 KiB
LLVM
; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v6 -global-isel %s -o - | FileCheck %s
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define void @test_void_return() {
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; CHECK-LABEL: test_void_return:
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; CHECK: bx lr
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entry:
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ret void
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}
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define i32 @test_constant_return_i32() {
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; CHECK-LABEL: test_constant_return_i32:
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; CHECK: mov r0, #42
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; CHECK: bx lr
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entry:
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ret i32 42
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}
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define zeroext i1 @test_zext_i1(i1 %x) {
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; CHECK-LABEL: test_zext_i1
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; CHECK: and r0, r0, #1
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; CHECK: bx lr
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entry:
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ret i1 %x
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}
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define signext i1 @test_sext_i1(i1 %x) {
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; CHECK-LABEL: test_sext_i1
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; CHECK: mov r1, #31
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; CHECK: lsl r0, r0, r1
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; CHECK: asr r0, r0, r1
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; CHECK: bx lr
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entry:
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ret i1 %x
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}
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define zeroext i8 @test_ext_i8(i8 %x) {
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; CHECK-LABEL: test_ext_i8:
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; CHECK: uxtb r0, r0
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; CHECK: bx lr
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entry:
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ret i8 %x
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}
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define signext i16 @test_ext_i16(i16 %x) {
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; CHECK-LABEL: test_ext_i16:
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; CHECK: mov r1, #16
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; CHECK: lsl r0, r0, r1
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; CHECK: asr r0, r0, r1
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; CHECK: bx lr
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entry:
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ret i16 %x
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}
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define void @test_trunc_i32_i16(i32 %v, i16 *%p) {
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; CHECK-LABEL: test_trunc_i32_i16:
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; The trunc doesn't result in any instructions, but we
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; expect the store to be explicitly 16-bit.
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; CHECK: strh r0, [r1]
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; CHECK: bx lr
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entry:
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%v16 = trunc i32 %v to i16
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store i16 %v16, i16 *%p
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ret void
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}
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define void @test_trunc_i32_i8(i32 %v, i8 *%p) {
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; CHECK-LABEL: test_trunc_i32_i8:
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; The trunc doesn't result in any instructions, but we
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; expect the store to be explicitly 8-bit.
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; CHECK: strb r0, [r1]
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; CHECK: bx lr
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entry:
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%v8 = trunc i32 %v to i8
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store i8 %v8, i8 *%p
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ret void
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}
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define i8 @test_add_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_add_i8:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_add_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_add_i16:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_add_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_add_i32:
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; CHECK: add r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = add i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_sub_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_sub_i8:
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; CHECK: sub r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = sub i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_sub_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_sub_i16:
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; CHECK: sub r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = sub i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_sub_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_sub_i32:
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; CHECK: sub r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = sub i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_mul_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_mul_i8:
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; CHECK: mul r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = mul i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_mul_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_mul_i16:
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; CHECK: mul r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = mul i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_mul_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_mul_i32:
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; CHECK: mul r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = mul i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_and_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_and_i8:
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; CHECK: and r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = and i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_and_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_and_i16:
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; CHECK: and r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = and i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_and_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_and_i32:
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; CHECK: and r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = and i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_or_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_or_i8:
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; CHECK: orr r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = or i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_or_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_or_i16:
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; CHECK: orr r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = or i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_or_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_or_i32:
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; CHECK: orr r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = or i32 %x, %y
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ret i32 %sum
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}
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define i8 @test_xor_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: test_xor_i8:
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; CHECK: eor r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = xor i8 %x, %y
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ret i8 %sum
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}
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define i16 @test_xor_i16(i16 %x, i16 %y) {
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; CHECK-LABEL: test_xor_i16:
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; CHECK: eor r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = xor i16 %x, %y
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ret i16 %sum
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}
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define i32 @test_xor_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: test_xor_i32:
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; CHECK: eor r0, r0, r1
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; CHECK: bx lr
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entry:
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%sum = xor i32 %x, %y
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ret i32 %sum
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}
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define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) {
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; CHECK-LABEL: test_stack_args_i32:
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; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
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; CHECK: ldr [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
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; CHECK: add r0, r2, [[P5]]
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; CHECK: bx lr
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entry:
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%sum = add i32 %p2, %p5
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ret i32 %sum
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}
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define i16 @test_stack_args_mixed(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4, i16 %p5) {
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; CHECK-LABEL: test_stack_args_mixed:
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; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4
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; CHECK: ldrh [[P5:r[0-9]+]], {{.*}}[[P5ADDR]]
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; CHECK: add r0, r1, [[P5]]
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; CHECK: bx lr
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entry:
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%sum = add i16 %p1, %p5
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ret i16 %sum
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}
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define i16 @test_stack_args_zeroext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i16 zeroext %p4) {
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; CHECK-LABEL: test_stack_args_zeroext:
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; CHECK: mov [[P4ADDR:r[0-9]+]], sp
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; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
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; CHECK: add r0, r1, [[P4]]
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; CHECK: bx lr
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entry:
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%sum = add i16 %p1, %p4
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ret i16 %sum
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}
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define i8 @test_stack_args_signext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 signext %p4) {
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; CHECK-LABEL: test_stack_args_signext:
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; CHECK: mov [[P4ADDR:r[0-9]+]], sp
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; CHECK: ldr [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
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; CHECK: add r0, r2, [[P4]]
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; CHECK: bx lr
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entry:
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%sum = add i8 %p2, %p4
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ret i8 %sum
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}
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define i8 @test_stack_args_noext(i32 %p0, i16 %p1, i8 %p2, i1 %p3, i8 %p4) {
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; CHECK-LABEL: test_stack_args_noext:
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; CHECK: mov [[P4ADDR:r[0-9]+]], sp
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; CHECK: ldrb [[P4:r[0-9]+]], {{.*}}[[P4ADDR]]
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; CHECK: add r0, r2, [[P4]]
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; CHECK: bx lr
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entry:
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%sum = add i8 %p2, %p4
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ret i8 %sum
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}
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define i32 @test_ptr_arg_in_reg(i32* %p) {
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; CHECK-LABEL: test_ptr_arg_in_reg:
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; CHECK: ldr r0, [r0]
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; CHECK: bx lr
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entry:
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%v = load i32, i32* %p
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ret i32 %v
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}
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define i32 @test_ptr_arg_on_stack(i32 %f0, i32 %f1, i32 %f2, i32 %f3, i32* %p) {
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; CHECK-LABEL: test_ptr_arg_on_stack:
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; CHECK: mov r0, sp
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; CHECK: ldr r0, [r0]
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; CHECK: ldr r0, [r0]
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; CHECK: bx lr
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entry:
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%v = load i32, i32* %p
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ret i32 %v
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}
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define i8* @test_ptr_ret(i8** %p) {
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; CHECK-LABEL: test_ptr_ret:
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; CHECK: ldr r0, [r0]
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; CHECK: bx lr
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entry:
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%v = load i8*, i8** %p
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ret i8* %v
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}
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define arm_aapcs_vfpcc float @test_float_hard(float %f0, float %f1) {
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; CHECK-LABEL: test_float_hard:
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; CHECK: vadd.f32 s0, s0, s1
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; CHECK: bx lr
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entry:
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%v = fadd float %f0, %f1
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ret float %v
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}
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define arm_aapcscc float @test_float_softfp(float %f0, float %f1) {
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; CHECK-LABEL: test_float_softfp:
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; CHECK-DAG: vmov [[F0:s[0-9]+]], r0
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; CHECK-DAG: vmov [[F1:s[0-9]+]], r1
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; CHECK: vadd.f32 [[FV:s[0-9]+]], [[F0]], [[F1]]
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; CHECK: vmov r0, [[FV]]
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; CHECK: bx lr
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entry:
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%v = fadd float %f0, %f1
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ret float %v
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}
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define arm_aapcs_vfpcc double @test_double_hard(double %f0, double %f1) {
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; CHECK-LABEL: test_double_hard:
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; CHECK: vadd.f64 d0, d0, d1
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; CHECK: bx lr
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entry:
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%v = fadd double %f0, %f1
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ret double %v
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}
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define arm_aapcscc double @test_double_softfp(double %f0, double %f1) {
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; CHECK-LABEL: test_double_softfp:
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; CHECK-DAG: vmov [[F0:d[0-9]+]], r0, r1
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; CHECK-DAG: vmov [[F1:d[0-9]+]], r2, r3
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; CHECK: vadd.f64 [[FV:d[0-9]+]], [[F0]], [[F1]]
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; CHECK: vmov r0, r1, [[FV]]
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; CHECK: bx lr
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entry:
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%v = fadd double %f0, %f1
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ret double %v
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}
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define arm_aapcscc i32 @test_cmp_i32_eq(i32 %a, i32 %b) {
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; CHECK-LABEL: test_cmp_i32_eq:
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; CHECK: mov [[V:r[0-9]+]], #0
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; CHECK: cmp r0, r1
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; CHECK: moveq [[V]], #1
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; CHECK: and r0, [[V]], #1
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; CHECK: bx lr
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entry:
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%v = icmp eq i32 %a, %b
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcscc i32 @test_cmp_ptr_neq(double *%a, double *%b) {
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; CHECK-LABEL: test_cmp_ptr_neq:
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; CHECK: mov [[V:r[0-9]+]], #0
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; CHECK: cmp r0, r1
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; CHECK: movne [[V]], #1
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; CHECK: and r0, [[V]], #1
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; CHECK: bx lr
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entry:
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%v = icmp ne double * %a, %b
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcscc i32 @test_cmp_i16_slt(i16 %a, i16 %b) {
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; CHECK-LABEL: test_cmp_i16_slt:
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; CHECK-DAG: mov [[V:r[0-9]+]], #0
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; CHECK: cmp r0, r1
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; CHECK: movlt [[V]], #1
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; CHECK: and r0, [[V]], #1
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; CHECK: bx lr
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entry:
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%v = icmp slt i16 %a, %b
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%r = zext i1 %v to i32
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ret i32 %r
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}
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define arm_aapcscc i32 @test_select_i32(i32 %a, i32 %b, i1 %cond) {
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; CHECK-LABEL: test_select_i32
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; CHECK: cmp r2, #0
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; CHECK: moveq r0, r1
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; CHECK: bx lr
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entry:
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%r = select i1 %cond, i32 %a, i32 %b
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ret i32 %r
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}
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define arm_aapcscc i32* @test_select_ptr(i32* %a, i32* %b, i1 %cond) {
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; CHECK-LABEL: test_select_ptr
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; CHECK: cmp r2, #0
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; CHECK: moveq r0, r1
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; CHECK: bx lr
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entry:
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%r = select i1 %cond, i32* %a, i32* %b
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ret i32* %r
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}
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define arm_aapcscc void @test_br() {
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; CHECK-LABEL: test_br
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; CHECK: [[LABEL:.L[[:alnum:]_]+]]:
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; CHECK: b [[LABEL]]
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entry:
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br label %infinite
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infinite:
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br label %infinite
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}
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declare arm_aapcscc void @brcond1()
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declare arm_aapcscc void @brcond2()
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define arm_aapcscc void @test_brcond(i32 %n) {
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; CHECK-LABEL: test_brcond
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; CHECK: cmp r0
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; CHECK-NEXT: movgt [[RCMP:r[0-9]+]], #1
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; CHECK: tst [[RCMP]], #1
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; CHECK-NEXT: beq [[FALSE:.L[[:alnum:]_]+]]
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; CHECK: bl brcond1
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; CHECK: [[FALSE]]:
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; CHECK: bl brcond2
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %if.true, label %if.false
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if.true:
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call arm_aapcscc void @brcond1()
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br label %if.end
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if.false:
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call arm_aapcscc void @brcond2()
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br label %if.end
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if.end:
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ret void
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}
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