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24 lines
786 B
LLVM
24 lines
786 B
LLVM
; RUN: llc < %s -march=avr | FileCheck %s
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; At one point, the 16-vit atomic load/store operations we defined in TableGen
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; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions.
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;
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; This would sometimes cause codegen to fail because LDDW requires 'PTRDISPREGS', and
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; so if we attempted to generate an atomic operation on the X register, it would hit
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; an assertion;
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%AtomicI16 = type { %UnsafeCell, [0 x i8] }
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%UnsafeCell = type { i16, [0 x i8] }
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; CHECK-LABEL: foo
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define i8 @foo(%AtomicI16*) {
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start:
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; We should not be generating atomics that use the X register, they will fail when emitting MC.
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; CHECK-NOT: X
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%1 = getelementptr inbounds %AtomicI16, %AtomicI16* %0, i16 0, i32 0, i32 0
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%2 = load atomic i16, i16* %1 seq_cst, align 2
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ret i8 0
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}
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