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103 lines
2.7 KiB
LLVM
103 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128:n8:16:32:64"
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
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; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: ret i32 [[TMP_3]]
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;
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%tmp.1 = and i32 %x, 65535
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%tmp.2 = xor i32 %tmp.1, -32768
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%tmp.3 = add i32 %tmp.2, 32768
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ret i32 %tmp.3
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 16
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; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: ret i32 [[TMP_3]]
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;
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%tmp.1 = and i32 %x, 65535
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%tmp.2 = xor i32 %tmp.1, 32768
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%tmp.3 = add i32 %tmp.2, -32768
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ret i32 %tmp.3
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}
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define i32 @test3(i16 %P) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[TMP_5:%.*]] = sext i16 %P to i32
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; CHECK-NEXT: ret i32 [[TMP_5]]
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;
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%tmp.1 = zext i16 %P to i32
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%tmp.4 = xor i32 %tmp.1, 32768
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%tmp.5 = add i32 %tmp.4, -32768
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ret i32 %tmp.5
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}
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define i32 @test4(i32 %x) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %x, 24
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; CHECK-NEXT: [[TMP_3:%.*]] = ashr exact i32 [[SEXT]], 24
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; CHECK-NEXT: ret i32 [[TMP_3]]
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;
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%tmp.1 = and i32 %x, 255
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%tmp.2 = xor i32 %tmp.1, 128
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%tmp.3 = add i32 %tmp.2, -128
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ret i32 %tmp.3
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}
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define i32 @test5(i32 %x) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: [[TMP_2:%.*]] = shl i32 %x, 16
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; CHECK-NEXT: [[TMP_4:%.*]] = ashr exact i32 [[TMP_2]], 16
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; CHECK-NEXT: ret i32 [[TMP_4]]
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;
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%tmp.2 = shl i32 %x, 16
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%tmp.4 = ashr i32 %tmp.2, 16
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ret i32 %tmp.4
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}
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; If the shift amount equals the difference in width of the destination
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; and source scalar types:
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; ashr (shl (zext X), C), C --> sext X
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define i32 @test6(i16 %P) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: [[TMP_5:%.*]] = sext i16 %P to i32
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; CHECK-NEXT: ret i32 [[TMP_5]]
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;
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%tmp.1 = zext i16 %P to i32
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%sext1 = shl i32 %tmp.1, 16
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%tmp.5 = ashr i32 %sext1, 16
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ret i32 %tmp.5
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}
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; Vectors should get the same fold as above.
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define <2 x i32> @test6_splat_vec(<2 x i12> %P) {
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; CHECK-LABEL: @test6_splat_vec(
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; CHECK-NEXT: [[ASHR:%.*]] = sext <2 x i12> %P to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[ASHR]]
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;
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%z = zext <2 x i12> %P to <2 x i32>
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%shl = shl <2 x i32> %z, <i32 20, i32 20>
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%ashr = ashr <2 x i32> %shl, <i32 20, i32 20>
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ret <2 x i32> %ashr
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}
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define i32 @test7(i32 %x) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: [[SUB:%.*]] = ashr i32 %x, 5
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; CHECK-NEXT: ret i32 [[SUB]]
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;
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%shr = lshr i32 %x, 5
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%xor = xor i32 %shr, 67108864
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%sub = add i32 %xor, -67108864
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ret i32 %sub
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}
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