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124 lines
4.5 KiB
LLVM
124 lines
4.5 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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; These are UB-free rotate left/right patterns that are narrowed to a smaller bitwidth.
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; See PR34046 and PR16726 for motivating examples:
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; https://bugs.llvm.org/show_bug.cgi?id=34046
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; https://bugs.llvm.org/show_bug.cgi?id=16726
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define i16 @rotate_left_16bit(i16 %v, i32 %shift) {
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; CHECK-LABEL: @rotate_left_16bit(
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %shift to i16
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; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
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; CHECK-NEXT: [[TMP3:%.*]] = sub i16 0, [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = and i16 [[TMP3]], 15
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i16 %v, [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = shl i16 %v, [[TMP2]]
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; CHECK-NEXT: [[CONV2:%.*]] = or i16 [[TMP5]], [[TMP6]]
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; CHECK-NEXT: ret i16 [[CONV2]]
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;
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%and = and i32 %shift, 15
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%conv = zext i16 %v to i32
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%shl = shl i32 %conv, %and
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%sub = sub i32 16, %and
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%shr = lshr i32 %conv, %sub
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%or = or i32 %shr, %shl
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%conv2 = trunc i32 %or to i16
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ret i16 %conv2
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}
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; Commute the 'or' operands and try a vector type.
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define <2 x i16> @rotate_left_commute_16bit_vec(<2 x i16> %v, <2 x i32> %shift) {
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; CHECK-LABEL: @rotate_left_commute_16bit_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = trunc <2 x i32> %shift to <2 x i16>
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; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i16> [[TMP1]], <i16 15, i16 15>
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; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i16> zeroinitializer, [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = and <2 x i16> [[TMP3]], <i16 15, i16 15>
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; CHECK-NEXT: [[TMP5:%.*]] = shl <2 x i16> %v, [[TMP2]]
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; CHECK-NEXT: [[TMP6:%.*]] = lshr <2 x i16> %v, [[TMP4]]
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; CHECK-NEXT: [[CONV2:%.*]] = or <2 x i16> [[TMP5]], [[TMP6]]
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; CHECK-NEXT: ret <2 x i16> [[CONV2]]
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;
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%and = and <2 x i32> %shift, <i32 15, i32 15>
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%conv = zext <2 x i16> %v to <2 x i32>
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%shl = shl <2 x i32> %conv, %and
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%sub = sub <2 x i32> <i32 16, i32 16>, %and
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%shr = lshr <2 x i32> %conv, %sub
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%or = or <2 x i32> %shl, %shr
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%conv2 = trunc <2 x i32> %or to <2 x i16>
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ret <2 x i16> %conv2
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}
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; Change the size, rotation direction (the subtract is on the left-shift), and mask op.
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define i8 @rotate_right_8bit(i8 %v, i3 %shift) {
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; CHECK-LABEL: @rotate_right_8bit(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i3 %shift to i8
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; CHECK-NEXT: [[TMP2:%.*]] = sub i3 0, %shift
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; CHECK-NEXT: [[TMP3:%.*]] = zext i3 [[TMP2]] to i8
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; CHECK-NEXT: [[TMP4:%.*]] = shl i8 %v, [[TMP3]]
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i8 %v, [[TMP1]]
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; CHECK-NEXT: [[CONV2:%.*]] = or i8 [[TMP4]], [[TMP5]]
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; CHECK-NEXT: ret i8 [[CONV2]]
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;
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%and = zext i3 %shift to i32
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%conv = zext i8 %v to i32
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%shr = lshr i32 %conv, %and
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%sub = sub i32 8, %and
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%shl = shl i32 %conv, %sub
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%or = or i32 %shl, %shr
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%conv2 = trunc i32 %or to i8
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ret i8 %conv2
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}
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; The shifted value does not need to be a zexted value; here it is masked.
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; The shift mask could be less than the bitwidth, but this is still ok.
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define i8 @rotate_right_commute_8bit(i32 %v, i32 %shift) {
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; CHECK-LABEL: @rotate_right_commute_8bit(
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %shift to i8
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; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 3
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; CHECK-NEXT: [[TMP3:%.*]] = sub nsw i8 0, [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP3]], 7
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; CHECK-NEXT: [[TMP5:%.*]] = trunc i32 %v to i8
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; CHECK-NEXT: [[TMP6:%.*]] = lshr i8 [[TMP5]], [[TMP2]]
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; CHECK-NEXT: [[TMP7:%.*]] = shl i8 [[TMP5]], [[TMP4]]
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; CHECK-NEXT: [[CONV2:%.*]] = or i8 [[TMP6]], [[TMP7]]
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; CHECK-NEXT: ret i8 [[CONV2]]
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;
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%and = and i32 %shift, 3
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%conv = and i32 %v, 255
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%shr = lshr i32 %conv, %and
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%sub = sub i32 8, %and
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%shl = shl i32 %conv, %sub
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%or = or i32 %shr, %shl
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%conv2 = trunc i32 %or to i8
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ret i8 %conv2
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}
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; If the original source does not mask the shift amount,
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; we still do the transform by adding masks to make it safe.
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define i8 @rotate8_not_safe(i8 %v, i32 %shamt) {
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; CHECK-LABEL: @rotate8_not_safe(
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %shamt to i8
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; CHECK-NEXT: [[TMP2:%.*]] = sub i8 0, [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP1]], 7
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; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP2]], 7
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i8 %v, [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = shl i8 %v, [[TMP3]]
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; CHECK-NEXT: [[RET:%.*]] = or i8 [[TMP5]], [[TMP6]]
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; CHECK-NEXT: ret i8 [[RET]]
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;
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%conv = zext i8 %v to i32
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%sub = sub i32 8, %shamt
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%shr = lshr i32 %conv, %sub
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%shl = shl i32 %conv, %shamt
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%or = or i32 %shr, %shl
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%ret = trunc i32 %or to i8
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ret i8 %ret
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}
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