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52 lines
1.9 KiB
TableGen
52 lines
1.9 KiB
TableGen
//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Backend internal SI Intrinsic Definitions. User code should not
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// directly use these.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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// Fully-flexible TBUFFER_STORE_FORMAT_* except for the ADDR64 bit, which is not exposed
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def int_SI_tbuffer_store : Intrinsic <
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[],
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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llvm_i32_ty, // num_channels(imm), selects opcode suffix: 1=X, 2=XY, 3=XYZ, 4=XYZW
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llvm_i32_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // dfmt(imm)
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llvm_i32_ty, // nfmt(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[]>;
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// Fully-flexible BUFFER_LOAD_DWORD_* except for the ADDR64 bit, which is not exposed
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def int_SI_buffer_load_dword : Intrinsic <
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[llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
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[llvm_anyint_ty, // rsrc(SGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_i32_ty, // soffset(SGPR)
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llvm_i32_ty, // inst_offset(imm)
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llvm_i32_ty, // offen(imm)
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llvm_i32_ty, // idxen(imm)
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llvm_i32_ty, // glc(imm)
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llvm_i32_ty, // slc(imm)
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llvm_i32_ty], // tfe(imm)
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[IntrReadMem, IntrArgMemOnly]>;
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} // End TargetPrefix = "SI", isTarget = 1
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