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131 lines
4.1 KiB
Python
131 lines
4.1 KiB
Python
# Test 32-bit COMPARE LOGICAL IMMEDIATE AND BRANCH in cases where the sheer
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# number of instructions causes some branches to be out of range.
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# RUN: python %s | llc -mtriple=s390x-linux-gnu | FileCheck %s
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# Construct:
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#
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# before0:
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# conditional branch to after0
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# ...
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# beforeN:
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# conditional branch to after0
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# main:
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# 0xffc6 bytes, from MVIY instructions
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# conditional branch to main
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# after0:
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# ...
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# conditional branch to main
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# afterN:
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#
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# Each conditional branch sequence occupies 14 bytes if it uses a short
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# branch and 20 if it uses a long one. The ones before "main:" have to
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# take the branch length into account, which is 6 for short branches,
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# so the final (0x3a - 6) / 14 == 3 blocks can use short branches.
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# The ones after "main:" do not, so the first 0x3a / 14 == 4 blocks
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# can use short branches. The conservative algorithm we use makes
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# one of the forward branches unnecessarily long, as noted in the
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# check output below.
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#
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 50
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# CHECK: jgl [[LABEL:\.L[^ ]*]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 51
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 52
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 53
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 54
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# CHECK: jgl [[LABEL]]
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# ...as mentioned above, the next one could be a CLIJL instead...
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 55
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clijl [[REG]], 56, [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clijl [[REG]], 57, [[LABEL]]
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# ...main goes here...
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clijl [[REG]], 100, [[LABEL:\.L[^ ]*]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clijl [[REG]], 101, [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clijl [[REG]], 102, [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clijl [[REG]], 103, [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 104
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 105
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 106
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# CHECK: jgl [[LABEL]]
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# CHECK: l [[REG:%r[0-5]]], 0(%r3)
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# CHECK: s [[REG]], 0(%r4)
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# CHECK: clfi [[REG]], 107
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# CHECK: jgl [[LABEL]]
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branch_blocks = 8
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main_size = 0xffc6
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print '@global = global i32 0'
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print 'define void @f1(i8 *%base, i32 *%stopa, i32 *%stopb) {'
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print 'entry:'
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print ' br label %before0'
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print ''
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for i in xrange(branch_blocks):
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next = 'before%d' % (i + 1) if i + 1 < branch_blocks else 'main'
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print 'before%d:' % i
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print ' %%bcur%da = load i32 , i32 *%%stopa' % i
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print ' %%bcur%db = load i32 , i32 *%%stopb' % i
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print ' %%bsub%d = sub i32 %%bcur%da, %%bcur%db' % (i, i, i)
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print ' %%btest%d = icmp ult i32 %%bsub%d, %d' % (i, i, i + 50)
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print ' br i1 %%btest%d, label %%after0, label %%%s' % (i, next)
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print ''
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print '%s:' % next
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a, b = 1, 1
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for i in xrange(0, main_size, 6):
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a, b = b, a + b
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offset = 4096 + b % 500000
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value = a % 256
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print ' %%ptr%d = getelementptr i8, i8 *%%base, i64 %d' % (i, offset)
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print ' store volatile i8 %d, i8 *%%ptr%d' % (value, i)
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for i in xrange(branch_blocks):
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print ' %%acur%da = load i32 , i32 *%%stopa' % i
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print ' %%acur%db = load i32 , i32 *%%stopb' % i
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print ' %%asub%d = sub i32 %%acur%da, %%acur%db' % (i, i, i)
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print ' %%atest%d = icmp ult i32 %%asub%d, %d' % (i, i, i + 100)
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print ' br i1 %%atest%d, label %%main, label %%after%d' % (i, i)
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print ''
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print 'after%d:' % i
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print ' %dummy = load volatile i32, i32 *@global'
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print ' ret void'
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print '}'
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