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44 lines
1.5 KiB
ArmAsm
44 lines
1.5 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// Invalid element kind.
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zip2 z6.h, z23.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
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// CHECK-NEXT: zip2 z6.h, z23.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Element size specifiers should match.
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zip2 z0.h, z30.h, z24.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: zip2 z0.h, z30.h, z24.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Too few operands
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zip2 z1.h, z2.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
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// CHECK-NEXT: zip2 z1.h, z2.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// z32 is not a valid SVE data register
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zip2 z1.s, z2.s, z32.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zip2 z1.s, z2.s, z32.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// p16 is not a valid SVE predicate register
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zip2 p1.s, p2.s, p16.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
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// CHECK-NEXT: zip2 p1.s, p2.s, p16.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Combining data and predicate registers as operands
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zip2 z1.s, z2.s, p3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zip2 z1.s, z2.s, p3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Combining predicate and data registers as operands
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zip2 p1.s, p2.s, z3.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
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// CHECK-NEXT: zip2 p1.s, p2.s, z3.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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