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197 lines
7.3 KiB
LLVM
197 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512vl,avx512bw | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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define <8 x i16> @test_llvm_x86_sse41_pmovsxbw(<16 x i8>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbw:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovsxbw (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovsxbw:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
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; AVX-NEXT: retq
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%3 = sext <8 x i8> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovsxbd(<16 x i8>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbd:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovsxbd (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovsxbd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
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; AVX-NEXT: retq
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%3 = sext <4 x i8> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovsxbq(<16 x i8>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovsxbq:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovsxbq (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovsxbq:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
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; AVX-NEXT: retq
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
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%3 = sext <2 x i8> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovsxwd(<8 x i16>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwd:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovsxwd (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovsxwd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
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; AVX-NEXT: retq
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%3 = sext <4 x i16> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovsxwq(<8 x i16>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovsxwq:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovsxwq (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovsxwq:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
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; AVX-NEXT: retq
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
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%3 = sext <2 x i16> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovsxdq(<4 x i32>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovsxdq:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovsxdq (%rdi), %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovsxdq:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
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; AVX-NEXT: retq
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%1 = load <4 x i32>, <4 x i32>* %a, align 1
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%3 = sext <2 x i32> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <8 x i16> @test_llvm_x86_sse41_pmovzxbw(<16 x i8>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbw:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovzxbw:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
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; AVX-NEXT: retq
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%3 = zext <8 x i8> %2 to <8 x i16>
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ret <8 x i16> %3
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovzxbd(<16 x i8>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbd:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovzxbd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
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; AVX-NEXT: retq
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%3 = zext <4 x i8> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovzxbq(<16 x i8>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovzxbq:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovzxbq:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero
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; AVX-NEXT: retq
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%1 = load <16 x i8>, <16 x i8>* %a, align 1
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%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
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%3 = zext <2 x i8> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <4 x i32> @test_llvm_x86_sse41_pmovzxwd(<8 x i16>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwd:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovzxwd:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
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; AVX-NEXT: retq
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%3 = zext <4 x i16> %2 to <4 x i32>
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ret <4 x i32> %3
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovzxwq(<8 x i16>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovzxwq:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovzxwq:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero
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; AVX-NEXT: retq
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%1 = load <8 x i16>, <8 x i16>* %a, align 1
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
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%3 = zext <2 x i16> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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define <2 x i64> @test_llvm_x86_sse41_pmovzxdq(<4 x i32>* %a) {
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; SSE41-LABEL: test_llvm_x86_sse41_pmovzxdq:
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; SSE41: ## %bb.0:
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; SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: test_llvm_x86_sse41_pmovzxdq:
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; AVX: ## %bb.0:
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; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; AVX-NEXT: retq
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%1 = load <4 x i32>, <4 x i32>* %a, align 1
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%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%3 = zext <2 x i32> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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