# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu                                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL

--- |
  define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
    %ret = mul i16 %arg1, %arg2
    ret i16 %ret
  }

  define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {
    %ret = mul i32 %arg1, %arg2
    ret i32 %ret
  }

  define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {
    %ret = mul i64 %arg1, %arg2
    ret i64 %ret
  }

...
---
name:            test_mul_i16
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: %edi, %esi

    ; ALL-LABEL: name: test_mul_i16
    ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY %di
    ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY %si
    ; ALL: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %ax = COPY [[IMUL16rr]]
    ; ALL: RET 0, implicit %ax
    %0(s16) = COPY %di
    %1(s16) = COPY %si
    %2(s16) = G_MUL %0, %1
    %ax = COPY %2(s16)
    RET 0, implicit %ax

...
---
name:            test_mul_i32
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: %edi, %esi

    ; ALL-LABEL: name: test_mul_i32
    ; ALL: [[COPY:%[0-9]+]]:gr32 = COPY %edi
    ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY %esi
    ; ALL: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %eax = COPY [[IMUL32rr]]
    ; ALL: RET 0, implicit %eax
    %0(s32) = COPY %edi
    %1(s32) = COPY %esi
    %2(s32) = G_MUL %0, %1
    %eax = COPY %2(s32)
    RET 0, implicit %eax

...
---
name:            test_mul_i64
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: %rdi, %rsi

    ; ALL-LABEL: name: test_mul_i64
    ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY %rdi
    ; ALL: [[COPY1:%[0-9]+]]:gr64 = COPY %rsi
    ; ALL: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY]], [[COPY1]], implicit-def %eflags
    ; ALL: %rax = COPY [[IMUL64rr]]
    ; ALL: RET 0, implicit %rax
    %0(s64) = COPY %rdi
    %1(s64) = COPY %rsi
    %2(s64) = G_MUL %0, %1
    %rax = COPY %2(s64)
    RET 0, implicit %rax

...