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external/llvm/test/CodeGen/RISCV/i32-icmp.ll
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184
external/llvm/test/CodeGen/RISCV/i32-icmp.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; TODO: check the generated instructions for the equivalent of seqz, snez,
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; sltz, sgtz map to something simple
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define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_eq:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp eq i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_ne:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp ne i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_ugt:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp ugt i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_uge:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp uge i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_ult:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: sltu a0, a0, a1
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp ult i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_ule:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: sltu a0, a1, a0
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp ule i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_sgt:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: slt a0, a1, a0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp sgt i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_sge:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: slt a0, a0, a1
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp sge i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_slt:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: slt a0, a0, a1
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp slt i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: icmp_sle:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: slt a0, a1, a0
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; RV32I-NEXT: xori a0, a0, 1
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%1 = icmp sle i32 %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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; TODO: check variants with an immediate?
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