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Imported Upstream version 5.18.0.225

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Former-commit-id: 10196d987d5fc5564b9d3b33b1fdf13190f4d0b5
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Xamarin Public Jenkins (auto-signing)
2018-12-21 19:01:49 +00:00
parent 32d52ae4ca
commit f32dbaf0b2
28477 changed files with 3866961 additions and 38 deletions
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36
external/llvm/test/CodeGen/PowerPC/vec_perf_shuffle.ll vendored Normal file
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; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep vperm
define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
%V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) {
%V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) {
%V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) {
%V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) {
%V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}