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Imported Upstream version 5.18.0.225

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Former-commit-id: 10196d987d5fc5564b9d3b33b1fdf13190f4d0b5
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Xamarin Public Jenkins (auto-signing)
2018-12-21 19:01:49 +00:00
parent 32d52ae4ca
commit f32dbaf0b2
28477 changed files with 3866961 additions and 38 deletions
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71
external/llvm/test/CodeGen/Mips/msa/shift-dagcombine.ll vendored Normal file
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
define void @ashr_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: ashr_v4i32:
%1 = ashr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sra
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
; CHECK-NOT: sra
store volatile <4 x i32> %1, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
%2 = ashr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sra
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -2
; CHECK-NOT: sra
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
ret void
; CHECK-LABEL: .size ashr_v4i32
}
define void @lshr_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: lshr_v4i32:
%1 = lshr <4 x i32> <i32 1, i32 2, i32 4, i32 8>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: srl
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 1
; CHECK-NOT: srl
store volatile <4 x i32> %1, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
%2 = lshr <4 x i32> <i32 -2, i32 -4, i32 -8, i32 -16>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: srl
; CHECK-DAG: addiu [[CPOOL:\$[0-9]+]], {{.*}}, %lo($
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0([[CPOOL]])
; CHECK-NOT: srl
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
ret void
; CHECK-LABEL: .size lshr_v4i32
}
define void @shl_v4i32(<4 x i32>* %c) nounwind {
; CHECK-LABEL: shl_v4i32:
%1 = shl <4 x i32> <i32 8, i32 4, i32 2, i32 1>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sll
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], 8
; CHECK-NOT: sll
store volatile <4 x i32> %1, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
%2 = shl <4 x i32> <i32 -8, i32 -4, i32 -2, i32 -1>,
<i32 0, i32 1, i32 2, i32 3>
; CHECK-NOT: sll
; CHECK-DAG: ldi.w [[R1:\$w[0-9]+]], -8
; CHECK-NOT: sll
store volatile <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R1]], 0($4)
ret void
; CHECK-LABEL: .size shl_v4i32
}