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Imported Upstream version 5.18.0.225

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Former-commit-id: 10196d987d5fc5564b9d3b33b1fdf13190f4d0b5
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Xamarin Public Jenkins (auto-signing)
2018-12-21 19:01:49 +00:00
parent 32d52ae4ca
commit f32dbaf0b2
28477 changed files with 3866961 additions and 38 deletions
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15
external/llvm/test/CodeGen/AMDGPU/fmin.ll vendored Normal file
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@ -0,0 +1,15 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = fcmp uge float %r0, %r1
%r3 = select i1 %r2, float %r1, float %r0
%vec = insertelement <4 x float> undef, float %r3, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)